Timer Circuits

This is an accurate long-duration time delay driver, switchable between 1 and 10 minutes or 10 to 100 minutes and whose function does not depend on electrolytic capacitors. Film dielectric caps have been selected. IC1 is configured as a free-running astable multivibrator which frequency is divided down by IC2, a 14020 (or 4020) CMOS 14-stage, ripple-carry binary divider.

IC2 (4017) is a CMOS decade counter IC, a five-stage Johnson counter with 10 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. This IC, together with IC3 and the 3-step rotary switch, can provide a maximum division ratio of 81,920 making it possible to time for periods up to 20 hours or so.

This application note uses a timer IC (ICL7555), CMOS logic and discrete transistors to automatically control the conversion the MAX190 12-bit SAR analog-to-digital converter (ADC). The delay between conversions can be programed using a resistor. Logic circuits ensures proper startup when power is applied.

With this circuit you can electronically simulate the noise of a diesel-train horn. The sound is triggered automatically as the train reaches a desired place on the track so you can produce the sound as the train approaches stations, level crossings, etc. The circuit can be built simply by using one 556 or two 555 timers. The rest of the parts are readily available and not critical. The output power from the two-Tone train horn is adequate to drive a miniature loudspeaker directly so all that is required is a single 9V alkaline battery or a 9VDC wall-adaptor.

The Link telephone intercom is designed around two ICs. The first, IC1, is an NE 556 dual timer chip, which is wired up to provide dial tone, ring tone (busy tone too, which will be explained along with a few add-ons to be mentioned later on) and ring pulses for the ringer circuit attached to each line circuit. The other chip, IC 2, is a CD 4017B decade counter, which is wired to count each train of dial pulses as they are received and buffered by the two opto-couplers, OC1 and OC 2 and their associated R/C networks.

A switched timer for intervals of 5 to 30 minutes incremented in 5 minute steps. Simple to build, simple to make, nothing too complicated here. However you must use the CMOS type 555 timer designated the 7555, a normal 555 timer will not work here due to the resistor values. Also a low leakage type capacitor must be used for C1, and I would strongly suggest a Tantalum Bead type.

A 555 timer can be used to generate a squarewave to produce a negative voltage relative to the negative battery terminal. When the timer output at pin 3 goes positive, the series 22 uF capacitor charges through the diode (D1) to about 8 volts. When the output switches to ground, the 22 uF cap discharges through the second diode (D2) and charges the 100 uF capacitor to a negative voltage. The negative voltage can rise over several cycles to about -7 volts but is limited by the 5.1 volt zener diode which serves as a regulator.

This is the square wave oscillation circuit which used NE555. 555 was developed as the IC for the precision timer. It is compactness (DIP 8 pins) and it is simple composition. It is often used for the timer circuit, the oscillation circuit because of precision well the operation.

The two timers determine the allowable accuracy for the timer IC under test. Potentiometers P1 and P2 permit ready adjustment for the desired range. With power applied, all timers switch to the high state and begin their cycles. The output of IC1 inhibits the flip-flop for the interval T1. At T2, the output of IC2 goes low and inhibits any signal from the timer under test. The period between T1 and T2 is the time alloted for IC3, the timer under test, to complete its cycle and produce a low output.

The two timers determine the allowable accuracy for the timer IC under test. Potentiometers P1 and P2 permit ready adjustment for the desired range. With power applied, all timers switch to the high state and begin their cycles. The output of IC1 inhibits the flip-flop for the interval T1. At T2, the output of IC2 goes low and inhibits any signal from the timer under test. The period between T1 and T2 is the time alloted for IC3, the timer under test, to complete its cycle and produce a low output.