One-shot-timer

  
This simple circuit consists of only two timing components Rr and Cr, the NE555, and bypass capacitor C2. While not essentiaHor operation, C2 is recommended for noise immunity. During standby, the trigger input terminal is held higher than 1/3 Vee and the output is low. When a trigger pulse appears with a level less than 1/3 Vce, the timer is triggered and the timing cycle starts. The output rises to a high level near Vcc. and at the same time, Crbegins to charge toward Vc·e·
One-shot-timer - schematic

When the Crvoltage crosses 2 /3 Vco the timing period ends with the output falling to zero, and the circuit is ready for another input trigger. Because of the internal latching mechanism, the timer will always time out when triggered, regardless of any subsequent noise, such as bounce, on the trigger input. For this reason, the circuit can also be used as a bounceless switch by using a shorter rc time constant. A 100-KO resistor for Rrand a 1-f."F capacitor for Cr would give a clean, 0.1 s output pulse when used as a bounceless switch.




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