Sequential-timer

  
The timer circuit shown gives independent control of the output`s on and off intervals, which can range from 0.055 seconds to 30 minutes, relatively unaffected by power-line transients. IC1 is a CMOS programmable-timer chip that includes 24 ripple-binary counter stages; the first eight are bypassed when logic 1 is applied to pin 6. Then, a 4-bit input code at pins A, B, C, and D connects one ofthe 16 remaining stages to the output at pin 13.
Sequential-timer - schematic

The chip includes an oscillator whose timing components are Cn Rn, and R 12. For this example, you adjust R n for an internal period TrN of 54.9 ms (18.2 Hz). Then, the output on or off interval is: ToUT ~ T1N 2 N-1, where N is the number of counter stages in the internal divider chaio (See Fig. 110-3). IC2 and IC3 are CMOS triple-spdt analog switches that connect one BCD code (A I-Dl) for the on interval and another (A2-D2) for the off interval. You can apply the codes using manual toggle switches or programmable latches. When power is first applied, the switches are in the positions shown, which applies A I -D1 to IC1 and generates the on interval. When the output changes state, all the switches change position and initiate the off interval by applying A2-D2 to IC1. The cycle then repeats. To eliminate race conditions, switches S1 and S2 of IC3 operate in sequence before the remaining four switches operate in parallel. To start the output sequence with an off instead of an on interval, connect a power-on-set signal at pin 1 instead of the power-on-reset signal at pin 2.




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