20Mhz-clock-phase-lock


Posted on Jul 14, 2012

The 20-MHz clock phase-locks to Apple`s Mac II 10-MHz NuBus clock. It uses a simple, inexpensive CMOS circuitry to generate 10-and 20-MHz square waves. The output duty cycle settings are insensitive to Vee variations. The input to the circuit is a NuBus clock signal with specifications that call for a 75 percent duty cycle at 10 MHz-a square wave that`s high for 75 ns and low for the remaining 25 ns.


20Mhz-clock-phase-lock
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To generate the 20-MHz signal, the circuit produces a 25-ns negative-going pulse, delayed 50 ns from the falling edge of the 10-MHz NuBus clock input at point E. NO Ring that pulse with the NuBus clock produces the 20-MHz clock at point G. Finally, applying the 25-ns pulse to the set input of a set-reset input, results in a 10-MHz square wave at F.




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