Clock Input Frequency Divider
Posted on Sep 8, 2012 10276
1. THE INPUT CLOCK frequency fed into this circuit is divided by 2n-l. The circuit consists of clocked flip-
flops and one exclusive-OR gate. The dt delay is zero in most cases. 2. THIS CIRCUIT CONFIGURATION divides the input frequency by three (a). The circuit"s timing diagram verifies the division (b). The input signal drives ICD. Because ICD"s positive input (V + ) is slightly offset to +0.1 V, its steady-state output will be near +13 V. This voltage is sent to ICC through D2, setting ICC"s output to +13 V. Therefore, point D is cut off by Dl, and CI is charged by the current source. Assuming the initial voltage on CI is zero, the maximum voltage (i7Cmnx) is given by: twdk > tPff+ dt+ tpxr+ tWff The right side of the inequality should be the minimum pulse width (either up time or down time) of the input clock. The circuit, when constructed with standard 74F-type parts, operates without any added delay in the exclusive-OR feedback path and with an input frequency of up to 22.5 MHz. The circuit"s output signal will have the same duty cycle as the input clock.