Posted on Apr 19, 2012 11164
This circuit produces a symmetrical waveform when dividing by either 2 or 3. The Divide Select input controls the
division factor. When Divide Select is high, flip-flops IC1 and IC2, along with associated gates, form the classical divide-by-3 circuit. When divide select is low, however, the output of the AND gate, IC5, goes low. Consequently, the NOR gate, IC4, inverts the feedback signal and passes it to the D input of the flip-flop, IC1. Now, IC1 acts like a toggle flip-flop and produces a divide-by-2 output. IC3, which is, in effect, a negative-edge-triggered flip-flop, provides symmetrical output signals. When you select division by 2 (Divide Select is low), the output and AND gate IC6 is low, and IC3 simply clocks out the divider"s output, delayed by one clock period. When you set Divide Select high, the path to the output through the AND and OR gates, IC6 and IC7, is enabled. This path means that the output goes high on the leading edge of IC3"s input (not its output) and produces a symmetrical divide-by-3 output.