Delay circuit of a multi-level output

  
As shown having a multi-stage delay circuit is output. The operational amplifier circuit used as comparators, operational amplifier A1 when the applied voltage-inverting input
Delay circuit of a multi-level output - schematic

+ VE, the operational amplifier A2, A3, A4-inverting input terminal voltage VC1 on the rise along an exponential curve rule. Inverting input of the operational amplifier a voltage is provided by a voltage divider classification. Therefore, each op amp input Vc1 from zero to + VB (power supply voltage) of t1, t2, t3 time, so that the output signals are inverted, enabling VA1, VA2, VA3 gradual delay purposes. Note that this circuit uses a dual power, namely the positive supply + VE, + VB and the negative supply -VB.




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