Delay line eases Spice dead-time generation


Posted on Oct 31, 2012

Generating complementary clock signals in a Spice simulation is an easy task. However, this task gets much harder if you need to introduce some dead time into the signals. This difficulty is especially true when you`re dealing with a variable-pulse-width-modulated switching cycle. In fact, you need to insert a dead-time interval between the switching of any two power devices in series, such as bridge or half-bridge designs that use MOSFETs and switch-mode power supplies and that implement synchronous rectification.






Leave Comment

characters left:

New Circuits

.

 


Popular Circuits

Remote control for lamp or appliance
Battery-Voltage Measuring Regulator
Self Retriggering Timed Generator Circuit
Schematic Diagram Car Amplifier for MP3
Bicycle Back Safety Light Circuit Schematic Circuit
Improved 3 Transistor Audio Amp (80 milliwatt) circuit
PIC Stepper Motor Tester
quick electronics designs
Softrock Lite II
It uses NAND gate transistor and humidity control circuit



Top