Feedback circuit eliminates CCD-driver delay mismatch

Posted on Oct 6, 2012

In a CCD (charge-coupled device), packets of charges shift across the array. The transistor array, also called a bucket-brigade shift register, receives drive from a dual-phase clock signal. Dual-phase clock signals comprise two synchronized clock signals that are 180° out of phase. High peak-output-current CCD drivers can buffer the logic-level clock signals and turn them into high-voltage and high-peak-current signals to drive the heavily capacitive gates of the many CCD transistors.

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