Digital-ad-capacitance-meter

  
The circuit charges and discharges a capacitor at a crystal-controlled rate, and stores on a sample-anddifference amplifier the change in voltage achieved. The current that flows during the discharge cycle is averaged, and ratiometrically measured in the a/d using the voltage change as a reference. Range switching is done by changing the cycle rate and current metering resistor. The cycle rate is synchronized with the conversion rate of the aid by using the externally divided internal oscillator and the internally divided back plane signals.
Digital-ad-capacitance-meter - schematic

For convenience in timing, the switching cycle takes 5 counter states, although only four switch configurations are used. Capacitances up to 200 p.F can be measured, and the resolution on the lowest range is down to 0.1 pF. The zero integrator time can be set initially at 1/3 to 112, the minimum auto-zero time, but if an optimum adjustment is reqnired, look at the comparator output with a scope under worst-case overload conditions. The output of the delay timer should stay low until after the comparator has come off the rail, and is in the linear region (usually fairly noisy).




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