High-speed-sample-and-hold

  
This circuit uses the speed and drive capability of the HA-5190 coupled with two high-speed DMOS FET switches. The input amplifier is allowed to operate at a gain of -5, although the overall circuit gain is unity.
High-speed-sample-and-hold - schematic

Acquisition times of less than 100 ns to 0.1% of a 1-V input step are possible. Drift current can be appreciably reduced by using FET input buffers on the output stage of the sample-and-hold.




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