Sample-and-hold

  
Two important properties of the 8043 are used to advantage in this circuit. The low input bias currents give rise to slow output decay rates (droop) in the hold mode, while the high slew rate at 6 V/p,s improves the tracking speed and the response time of the circuit. The upper waveform is the input 10 V/div, the lower waveform the output 5 V /div. The logic input is high.
Sample-and-hold - schematic

The center waveform is the analog input, a ramp moving at about 67 V/ms, the lower waveform is the logic input to the sample-and-hold; a logic 1 initiates the sample mode. The upper waveform is the output, displaced by about one scope division 2 V from the input to avoid superimposing traces. The hold mode, during which the output remains constant, is clearly visible. At the beginning of a sample period, the output takes about 8 p,s to catch up with the input, after which it tracks, until the next hold period.




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