MSF Radio Receiver
This document describes an earlier version of a project that has been found to be quite unreliable. The project is ongoing, with periodic updates being posted until a proper design and rig are developed, at which point a new page will be created. Current Status (January 2010): Progress has been made on a dsPIC superheterodyne design, with a test rig established that includes a PIC-controlled variable frequency oscillator (VFO) and an LCD interface. Future work will focus on implementing a tuning mechanism and a Huff-Puff stabilizer for the VFO in firmware, as well as designing the crystal filter and amplifier hardware blocks. Current Status (October 2009): A single-pole crystal filter was found to be unreliable due to its narrow bandwidth, which causes slow on-off transitions that prevent the carrier from decaying, making it unsuitable for double bit transmissions. Although attempts were made to improve transitions by lowering crystal termination impedance, this adversely affected filtering properties. A dsPIC-based superheterodyne design is being considered, using two NE602 mixers and higher frequency crystals, which are more cost-effective than low-frequency crystals and inductors that were previously used. Current Status (June 2009): Following discussions, work has progressed on a DSP algorithm intended for use with a dsPIC30F2010, pending the design of a suitable hardware front-end. A single-pole crystal filter is planned to enhance selectivity and minimize overload risks from out-of-band signals, though challenges remain in achieving this. A frequency counter and standard are also needed for accurate measurement of crystal parameters. Current Status (January 2009): The detector and TTL output stages require redesign due to reliability issues with the PCB assembly. The project is on hold pending a better PCB production method, which should enhance board quality and reduce errors. The initial assembly did not meet quality expectations, and the detector's performance diverged significantly from breadboard testing. This is the first attempt at a radio receiver and PCB design, with Version 2 of the receiver being detailed here. Version 1 failed after assembly, despite functioning well on a breadboard. The new design eliminates the pre-amp and RF band-pass filter, allowing the signal to pass directly from the antenna tuned circuit to the mixer. The IF filter has been redesigned as a 4-pole, low-pass, active Chebyshev filter, with an adjustable gain amplifier added to prevent overload from strong signals. The project aims to learn the intricacies of radio receiver design without resorting to pre-built modules. The MSF Radio Clock signal at Rugby (now Anthorn) is the intended target, but the project has proven more complex than anticipated. The goal is to develop a radio receiver and eventually create an MSF decoder, which may utilize a Z80-based system interfacing with a PC or a series of PIC chips. The receiver is designed as a Direct Conversion (DC) receiver, having abandoned earlier attempts at Tuned Radio Frequency (TRF) receivers due to complexity and error-proneness in cascading filters. The MSF signal is transmitted on a 60KHz carrier using On-Off Keying (OOK) to convey data.
The project involves several key components and design considerations essential for the successful implementation of a Direct Conversion receiver. The architecture is chosen for its simplicity and efficiency in demodulating the MSF signal, which operates at a low frequency of 60KHz. The core of the receiver consists of a mixer stage, where the incoming RF signal is mixed with a local oscillator signal generated by the PIC-controlled VFO. The use of NE602 mixers is advantageous due to their integrated features that facilitate signal conversion while maintaining low noise levels.
The design incorporates a crystal filter to enhance selectivity and suppress unwanted out-of-band signals. The transition from a single-pole to a 4-pole Chebyshev filter is a significant improvement, as it provides better attenuation of out-of-band signals while maintaining a flat passband response. The adjustable gain amplifier is critical for adapting to varying signal strengths, ensuring that the receiver can handle both weak and strong signals without distortion or overload.
The DSP algorithm developed in Octave will be implemented on the dsPIC30F2010 microcontroller, which is capable of handling the necessary signal processing tasks. The design also requires a frequency counter to accurately measure crystal parameters, aiding in the optimization of the filter design.
Overall, the project aims to provide a comprehensive educational experience in radio receiver design, addressing the challenges encountered in earlier versions and leveraging modern components and techniques to create a robust and reliable receiving system. The eventual goal includes the development of an MSF decoder, which will involve further integration with microcontroller technology to maintain accurate time synchronization with the broadcast signal.This page documents an older version of the project that proved very unreliable. This is (still) an ongoing project when I get free time, so I post periodic updates here until I get a proper design/rig and eventually create a new page for it (with pictures of course. ) Current Status (January 2010): During the time off at Christmas I`ve made some r eal progress on my dsPIC superhet design. Still a fair way to go, but I have a test rig knocked up with a PIC-controlled VFO and LCD interface among other things. The next stages - when time permits - will be implementing a proper tuning mechanism and the Huff-Puff stabiliser for the VFO (both in firmware), and then designing the crystal filter and amplifier hardware blocks.
Eventually, I will create a page for the project that will replace this one. Current Status (October 2009): I have found a single-pole crystal filter to be unreliable - the bandwidth is far too narrow so the on-off transitions are so slow that the carrier never decays; this is no good for the double bit transmissions. I`ve also discovered that the transitions can be improved by lower crystal termination impedance, but that`s more crystal drive and it wrecks the filtering properties.
This is no good, especially when the receiver is supposed to operate in a noisy PC room; a better way needs to be found. I`m toying with the idea of a simple dsPIC-based superhet; two NE602 mixers (one for up-conversion for filtering, one for converting back to baseband) and a few higher frequency crystals (greater bandwidth and more design info available) come to about the same cost as the low-frequency crystals plus the number of inductors I was using for low-Q pre-crystal filtering.
Besides which, the inductors tended to pick up a lot of noise and the filters needed even more poles to provide significant attenuation. Superhet here I come. Current Status (June 2009): After various discussions on the PIC List, I have done a little work on this project since the last update.
I have a working Octave model of a DSP algorithm which I intend to use with a dsPIC30F2010 once I design a suitable hardware front-end. I am hoping to use a simple crystal filter (single pole) to increase the initial selectivity and reduce the likelihood of overloading the gain stages due to out-of-band signals, but have yet to figure out how to get this to work.
The design details of single pole crystal filters are a little hard to come by on the `net. I also need to create a frequency counter and frequency standard so that the crystal parameters can be measured, since the datasheets are not terribly helpful in this regard. Current Status (January 2009): Unfortunately the detector/TTL output stages need to be redesigned (or tweaked), since they are not working reliably now that the board has been assembled on a PCB.
The project is on hold until a I obtain a better method of PCB production (possibly CNC). This should make it easier to produce boards, less error prone and more time efficient. Plus the health benefits of not having to spend time in a dark room coating boards with photo resist (even with a gask mask it`s not nice. ) Overall, it`s a little disappointing that the board is not as good quality as I`d hoped and that the detector works significantly differently than on the breadboard - I`ll improve on these factors in due course.
This is my first stab at a radio receiver - in fact it`s pretty much my first proper electronics project, and also my first PCB (so please don`t laugh too hard at the design. ) This page details Version 2 of the receiver, as Version 1 stopped working once I assembled it onto a PCB (although the damn thing worked continuously for 3 months on the breadboard in my noisy computer room.
) I think the failure was due, in part, to not having enough trimmable elements to tune it once assembled; and the other part due to a poor front-end design. This new circuit differs from the original as I have removed the pre-amp and RF band-pass filter so that the signal is passed pretty much straight from the antenna tuned circuit to the mixer.
I also decided to re-design the IF filter, but this time I opted for a 4-pole, low-pass, active Chebyshev filter rather than a two-pole passive Butterworth band-pass, and I added an amplifier of adjustable gain to prevent overloading when the signal is strong, rather than the very high-gain single op-amp amplifier I had before. I was told - by somebody who knows rather more about electronics than I do - that a receiver for the MSF Radio Clock signal at Rugby (now Anthorn) would be a doddle, so I thought it would be a good starter project.
As it turns out, it`s a little more complicated than I anticipated. The object of the exercise is to learn how to design and build a radio receiver, so I decided not to buy a pre-built module (such as those made by Galleon) and have shied away from monolithic receiver chips such as the MK484. I did look around for existing designs on the `net, but there seems to be precious little available - especially if you don`t intend to use a pre-built module of some sort.
The best example I have found is Hans Summers` project, but by his own admission it`s not a very good receiver. Hans` site is well worth a look - he seems to be a very interesting fellow that`s done some fantastic (and crazy.
) projects. As a result, I give my MSF offering to the `net, in the hope that somebody will find it useful, play with it, tweak it, hack it, and share with the rest of us. This is a two-part project and eventually I intend to build the MSF decoder, which will be a Z80-based system that will interface with my PC and keep its clock correct.
The firmware for the Z80 decoder will be written in assembly, for which I am building an assembler - again, this is another learning exercise, and I am well aware of the plethora of existing assemblers. Or perhaps the decoder will be a bunch of PIC chips rather than a Z80-based system. or something completely different. I`ve got plenty of time to think about it. This receiver is a Direct Conversion (DC) receiver. I settled on this architecture after initially trying a Tuned Radio Frequency (TRF) receiver and finding that it was a pain - and fraught with error - trying to cascade the necessary filters.
In the very beginning I looked at Regenerative and Super Regenerative receivers also, but decided that the former was not stable enough over time without periodic adjustments, and the latter was just not what I thought it was. The MSF signal is broadcast on a 60KHz carrier, which is On-Off-Keyed (OOK) to transmit 2 bits of data per second.
The full specification for the signal can be found on the National Physics Laboratory `s homepage, but I think that the Wikipedia article is a better place to start. The receiver can be broken down into distinct blocks, . 🔗 External reference
The project involves several key components and design considerations essential for the successful implementation of a Direct Conversion receiver. The architecture is chosen for its simplicity and efficiency in demodulating the MSF signal, which operates at a low frequency of 60KHz. The core of the receiver consists of a mixer stage, where the incoming RF signal is mixed with a local oscillator signal generated by the PIC-controlled VFO. The use of NE602 mixers is advantageous due to their integrated features that facilitate signal conversion while maintaining low noise levels.
The design incorporates a crystal filter to enhance selectivity and suppress unwanted out-of-band signals. The transition from a single-pole to a 4-pole Chebyshev filter is a significant improvement, as it provides better attenuation of out-of-band signals while maintaining a flat passband response. The adjustable gain amplifier is critical for adapting to varying signal strengths, ensuring that the receiver can handle both weak and strong signals without distortion or overload.
The DSP algorithm developed in Octave will be implemented on the dsPIC30F2010 microcontroller, which is capable of handling the necessary signal processing tasks. The design also requires a frequency counter to accurately measure crystal parameters, aiding in the optimization of the filter design.
Overall, the project aims to provide a comprehensive educational experience in radio receiver design, addressing the challenges encountered in earlier versions and leveraging modern components and techniques to create a robust and reliable receiving system. The eventual goal includes the development of an MSF decoder, which will involve further integration with microcontroller technology to maintain accurate time synchronization with the broadcast signal.This page documents an older version of the project that proved very unreliable. This is (still) an ongoing project when I get free time, so I post periodic updates here until I get a proper design/rig and eventually create a new page for it (with pictures of course. ) Current Status (January 2010): During the time off at Christmas I`ve made some r eal progress on my dsPIC superhet design. Still a fair way to go, but I have a test rig knocked up with a PIC-controlled VFO and LCD interface among other things. The next stages - when time permits - will be implementing a proper tuning mechanism and the Huff-Puff stabiliser for the VFO (both in firmware), and then designing the crystal filter and amplifier hardware blocks.
Eventually, I will create a page for the project that will replace this one. Current Status (October 2009): I have found a single-pole crystal filter to be unreliable - the bandwidth is far too narrow so the on-off transitions are so slow that the carrier never decays; this is no good for the double bit transmissions. I`ve also discovered that the transitions can be improved by lower crystal termination impedance, but that`s more crystal drive and it wrecks the filtering properties.
This is no good, especially when the receiver is supposed to operate in a noisy PC room; a better way needs to be found. I`m toying with the idea of a simple dsPIC-based superhet; two NE602 mixers (one for up-conversion for filtering, one for converting back to baseband) and a few higher frequency crystals (greater bandwidth and more design info available) come to about the same cost as the low-frequency crystals plus the number of inductors I was using for low-Q pre-crystal filtering.
Besides which, the inductors tended to pick up a lot of noise and the filters needed even more poles to provide significant attenuation. Superhet here I come. Current Status (June 2009): After various discussions on the PIC List, I have done a little work on this project since the last update.
I have a working Octave model of a DSP algorithm which I intend to use with a dsPIC30F2010 once I design a suitable hardware front-end. I am hoping to use a simple crystal filter (single pole) to increase the initial selectivity and reduce the likelihood of overloading the gain stages due to out-of-band signals, but have yet to figure out how to get this to work.
The design details of single pole crystal filters are a little hard to come by on the `net. I also need to create a frequency counter and frequency standard so that the crystal parameters can be measured, since the datasheets are not terribly helpful in this regard. Current Status (January 2009): Unfortunately the detector/TTL output stages need to be redesigned (or tweaked), since they are not working reliably now that the board has been assembled on a PCB.
The project is on hold until a I obtain a better method of PCB production (possibly CNC). This should make it easier to produce boards, less error prone and more time efficient. Plus the health benefits of not having to spend time in a dark room coating boards with photo resist (even with a gask mask it`s not nice. ) Overall, it`s a little disappointing that the board is not as good quality as I`d hoped and that the detector works significantly differently than on the breadboard - I`ll improve on these factors in due course.
This is my first stab at a radio receiver - in fact it`s pretty much my first proper electronics project, and also my first PCB (so please don`t laugh too hard at the design. ) This page details Version 2 of the receiver, as Version 1 stopped working once I assembled it onto a PCB (although the damn thing worked continuously for 3 months on the breadboard in my noisy computer room.
) I think the failure was due, in part, to not having enough trimmable elements to tune it once assembled; and the other part due to a poor front-end design. This new circuit differs from the original as I have removed the pre-amp and RF band-pass filter so that the signal is passed pretty much straight from the antenna tuned circuit to the mixer.
I also decided to re-design the IF filter, but this time I opted for a 4-pole, low-pass, active Chebyshev filter rather than a two-pole passive Butterworth band-pass, and I added an amplifier of adjustable gain to prevent overloading when the signal is strong, rather than the very high-gain single op-amp amplifier I had before. I was told - by somebody who knows rather more about electronics than I do - that a receiver for the MSF Radio Clock signal at Rugby (now Anthorn) would be a doddle, so I thought it would be a good starter project.
As it turns out, it`s a little more complicated than I anticipated. The object of the exercise is to learn how to design and build a radio receiver, so I decided not to buy a pre-built module (such as those made by Galleon) and have shied away from monolithic receiver chips such as the MK484. I did look around for existing designs on the `net, but there seems to be precious little available - especially if you don`t intend to use a pre-built module of some sort.
The best example I have found is Hans Summers` project, but by his own admission it`s not a very good receiver. Hans` site is well worth a look - he seems to be a very interesting fellow that`s done some fantastic (and crazy.
) projects. As a result, I give my MSF offering to the `net, in the hope that somebody will find it useful, play with it, tweak it, hack it, and share with the rest of us. This is a two-part project and eventually I intend to build the MSF decoder, which will be a Z80-based system that will interface with my PC and keep its clock correct.
The firmware for the Z80 decoder will be written in assembly, for which I am building an assembler - again, this is another learning exercise, and I am well aware of the plethora of existing assemblers. Or perhaps the decoder will be a bunch of PIC chips rather than a Z80-based system. or something completely different. I`ve got plenty of time to think about it. This receiver is a Direct Conversion (DC) receiver. I settled on this architecture after initially trying a Tuned Radio Frequency (TRF) receiver and finding that it was a pain - and fraught with error - trying to cascade the necessary filters.
In the very beginning I looked at Regenerative and Super Regenerative receivers also, but decided that the former was not stable enough over time without periodic adjustments, and the latter was just not what I thought it was. The MSF signal is broadcast on a 60KHz carrier, which is On-Off-Keyed (OOK) to transmit 2 bits of data per second.
The full specification for the signal can be found on the National Physics Laboratory `s homepage, but I think that the Wikipedia article is a better place to start. The receiver can be broken down into distinct blocks, . 🔗 External reference
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