Delayed pulse generator

  
The circuit offers independent control of initial delay and pulse rate. ICIc is connected as a pulse generator whose operation is inhibited by the normally low O/P of the ICla. When the circuit input goes low i.e., by pressing PB1, IClb O/P goes high and the circuit O/P goes low thus replicating the input. When the input is kept low capacitor Cl charges via R2 to a point where ICla O/P goes low. This allows the pulse generator ICIc to start and `rapid fire` pulses appear at the circuit O/P. When the circuit input returns to the high state Cl is rapidly discharged viaD1 and Rl.
Delayed pulse generator  - schematic

The value of R2 and Cl control the initial delay while R3 and C2 control the pulse rate. The values given will give a delay of around 0.5 seconds and a pulse rate of 200/300 Hz depending on supply voltage. PB1 may be replaced by an open collector TTL gate or a common emitter transistor stage if required.




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