Posted on Jan 26, 2013

An input signal drives both SN74 74 D-type flip-flops, which are positive edge-triggered devices. A low-to-high input signal transition triggers tbe A flip-flop, while a high-to-low input signal transition triggers the B flip-flop via tbe SN7404 inverter. Either flip-flop in tbe high state will cause the output to decrease via the SN7402 NOR gate. This in turn disables the opposite flip-flop from going to tbe high state. The flipflop in the high state remains there for one clock period, then it is clocked low. Witb both flip-flops low, the output increases, enabling the opposite flip-flop to be clocked high one-half clock cycle later.

Click here to download the full size of the above Circuit.

This alternate enabling and disabling action of the flip-flops results in a divide-by-1112 function. That is, three clock pulses in, produce two evenly spaced clock pulses out. The circuit has no lock-up states and no inherent glitches. Replacing the NOR gate with an SN7400 NAND gate inverts the A, B, and output signals. By adding simple binary or BCD counters, counting chains, such as divide-by-3, -6, -12, -24, -15, -30, etc., can be generated using the divide-by-11/z circuit as a basis.

Leave Comment

characters left:

New Circuits



Popular Circuits

Audio sine-wave generator
Overtone crystal oscillator
Three Phase 6 Pulse Inverter
Cordless Phone Backup
Low Cost Dimmable Led Ballast Using The Valley Fill Current Shaping Circuit
Electronic Siren Circuit
Build a Miniature High-Rate Speed Control with Battery Eliminator Circuit (BEC)
One way to prevent reverse polarity of the DC power supply circuit
Basic circuit diagram connection of signal and power ISO103
555 logic test circuit diagram pen
LM1877 amplifier having a control circuit diagram of the bass