This circuit, shown symmetrically, divides an input by virtually any odd number. The circuit counts n + 1/2 clocks twice to achieve the desired divisor. By selecting the proper n, which is tbe decoded output of the LS161 counter, you can obtain divisors from 3 to 31. The circuit, as shown, divides by 25; you can obtain higher divisors by cascading additional LS161 counters. The counter and IC5A form the n + 1 /z counter. Once the counter reaches the decoded count, n, IC5A ticks off an additional 1/z clock, which clears the counter and puts it in hold.
Additionally, IC5A clocks IC5B, which changes the clock phasing through the XOR gate, IC1. The next edge of the input clocks IC5A, which reenables the counter to start counting for an additional n + "lz cycles. Although the circuit has been tested at 16 MHz, a worst-case timing analysis reveals that tbe maximum input frequency is between 7 and 8 MHz.