An exclusive-OR gate, IClD, turns a simple CMOS oscillator into an FSK generator. When the data input increases, IClD inverts, and negative feedback through R2 lowers the circuit`s output frequency. A low input results in positive feedback and a higher output frequency. Rl and C set the oscillator`s frequency range, and R2 determines the circuit`s frequency shift.

To ensure frequency stability, make R3 much greater than Rl and use a high-quality feedback capacitor. The three gates constituting the oscillator itself need not be exclusive- OR types; use any CMOS inverter.

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