VCO with NE567

  
Who would like to build a sidetone oscillator with a minimum amount of parts should try the NE567 integrated circuit. The NE567 is a PLL circuit with an internal VCO for a operating frequency less than 500 kHz and it is normally used as an audio tone decoder. The VCO frequency is adjustable by two passive components only. For a 750 Hz sidetone in an amateur radio application the capacitor C1 and the resistor R1 define the VCO frequency. The IC supplier allows for R1 a range of 2 .... 20 kOhm. The sidetone can be taken from pin 6 as a symmetrical triangle signal or as a high impedance square wave signal from pin 5. The triangle signal has an amplitude of 1 Vss and the square wave signal of 2 Vss. In order to switch on the oscillator during transmit mode Tx, one can connect pin 7 to Gnd or pin 4 to Vcc. Pins 1, 2, 3 and 8 remain free (nc).
VCO with NE567 - schematic

VCO with NE567 - img1

The permissible supply voltage Vcc is +4 V to +10 V. With about 6 mA at Vcc = +5 V the IC is relatively economically in its current consumption. The second sidetone oscillator is build up completely discrete with two transistors and four passive components. The VT1 and VT2 arrangement corresponds to the thyristor substitute circuit, but with something special. Not the emitter of VT2 but the VT2 collector is connected to Gnd potential. If one runs VT2 as usual with the emitter connected to ground, VT1 and VT2 together have a very high current gain. This high gain causes that the low current flow through R1 (C1 is discharged via VT1) is sufficient high that both transistors remain in the on state. Hence periodically charging and discharging the capacitor is impossible, because the hold on current will never be fallen below. A measure against this effect could be a low impedance voltage divider R2/R3 in order to take over a partial current (Ic_VT2) or a gain reduction. The later is achieved very easy with the reverse operation of VT2. The hold on current is fallen and thus VT1 and VT2 return to the off state after discharging C1. Now the circuit operates as planed. C1 will be charged by a low current via R1 up to the voltage rate Uc = Ux + 0,7 V. A small basis current flows into VT1 as soon as Uc exceeds the limit value Ux + 0,7 V. VT2 conducts too by the now starting collector current. On the basis of the positive feedback...



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