Posted on Jul 6, 2012

At startup, the voltage in the trigger input at pin 2 is less than the trigger level voltage, `13 VDD. caus ing the timer to be triggered via pin 2. The output of the timer at pin 3 becomes high, allowing capacitor c, to charge very rapidly through diode Dl and resistor Rl. When capacitor C, charges to the upper threshold voltage 2 /3 V00, the flip-flop is reset, the output at pin 3 decreases, and capacitor C, discharges through the current mirror, TLOll.

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When the voltage at pin 2 re-dches 1/3 VDD. the lower threshold or trigger level, the timer triggers again and the cycle is repeated.

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