Posted on Mar 23, 2013 4369
This relatively simple, inexpensive circuit requiring one trimming operation can multiply or divide with a consistentaccuracy of greater than 1 part in 1,000. An inexpensive CMOS version of standard 555 timer chip T, in conjunction with low-drift LMll error amplifier A3, an inexpensive analog chopper switch SW, form a unique voltage-to-duty-cycle converter to produce the difficult transfer function necessary for accurate conversion.
An unknown multiplicand voltage applied to the A3 error op amp circuit"s Y input controls the duty cycle of the timer through its pin 5 modulation input. The network between the sink-and-source output of the timer, pin 3, and the state trigger inputs, pins 2 and 6, cause the timer to oscillate. An error feedback signal from the timer"s discharge output, pin 7, represents the duty cycle. Integrating this duty-cycle signal with voltage reference REF representing full scale, and applying the result to the inverting input of A3, closes the feedback loop and insures high accuracy. Multiplier X feeds into another LMll op amp, A1, which acts as a input buffer and scaler. A third LMll, A2, filters and buffers the Z output. Between A1 and A2, the timer"s duty-cycle output modulates the analog switches of a CD4066 to achieve the desired multiplier output. To perform division instead of multiplication, reconfigure the op amp A1 circuit with the use of jumpers. Amplifier A2 isn"t required in the division configuration. To calibrate the circuit, connect the X andY inputs together and apply 10 V. Then adjust the 10-turn span potentiometer to achieve a 10-V output at Z for multiplication, or 1 V for the division configuration. Also check for zero output at a zero multiplier input. The circuit is scaled for 0 -10 V inputs and outputs with a small overrage capability, but other scalings are possible. Star grounding or a heavy ground bus should be used to reduce offset problems that are unavoidable in this design.