Peak voltage sample and hold circuit

Posted on Mar 28, 2007

Peak voltage sample and hold circuit: peak voltage sample and hold circuit is shown in Figure 12-50. Peak voltage sample and hold circuit south chip sample and hold chip LF398 and a voltage comparator LM311 constitution. LF398 output and input voltages

Peak voltage sample and hold circuit
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LM3J1 by comparing t When U. Uo time. LM311 output high, to LF398 logic control terminal 8 feet, LF398 in the sampling state state} When Ul peak and decline, U, <U., Output low voltage comparator LM311, LF398: Logic control terminal set to low level, so LF398 hold. Since the LM311 use open collector output, so an pull-up resistor. By the overvoltage detection circuit output terminal sent pulse control circuit switch is turned on, the sampling capacitor discharges never had electricity, otherwise sampling circuit has been tracking the peak change.

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