Decoding 4 buttons with two I/O's on AVR

Posted on Aug 17, 2012

Just the solution for AVR applications in which I/O is tight, such as the ATtiny12. This should work well on other kids of controllers that have independently controlled I/O direction registers, such as PIC and 6805 controllers. This is a solution was devised for those I/O limited 8 pin controllers like the AT90S2323 (though I tested it on an AT90S1200A). In principle, the circuit senses three states of the pushbuttons: Open (no button down), Pulled Up, and Pulled Down. The process is this: Pin A (PORTB bit 4)driven high through a resistor and the other end of the resistor is looked, at Pin B (PORTB bit 4) to see if it is being pulled high, low, or not being driven up a button at all. Then Pin B is driven and the other end of the resistor (Pin A) is looked at.

Decoding 4 buttons with two I/O's on AVR
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In the circuit, a 39k resistor is placed across the two I/O pins to allow each pin to drive the other through the resistor. The two pair of buttons connected identically, except that one pair of buttons is connected to pin A (PORTB bit 3) and the other pair of buttons is connected Pin B (PORTB bit 4). In each pair, one button is connected to VCC through a 10k resistor and the other button connects to ground through a 10k resistor. The remaining contacts on the two buttons in each pair are connected together and connected to their respective I/O pin. Its a digital circuit so the actual resistor values aren't important as long as the logic thresholds for the input ports are exceeded. The four button implementation only requires three resistors total. This concept can be extended by using more pairs of I/O pins and still has an advantage over simpler matrices, but the disadvantage disappears when the number of I/O lines reaches 8. (Added June, 2003): One other note: A circuit was published on the web around the end of 2002 (about a year after this circuit was first published) that uses one less resistor but relies on the value of the weak internal pullup on the processor's I/O pin. I rejected this concept early on as it was not robust enough in light of the poorly defined characteristics of the weak pullup. The design presented here will work by design.

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