Frequency comparator circuit

  
Input 1 is used as a gating period, during which a single rising edge on input 2 will cause a logic 1 output-any other number, indicating non-identical frequencies causes a logic 0 output. ICla converts input 1 to a narrow pulse which initializes IC2 which forms a two-stage shift register clocked by input 2. On the first edge of input 2 a logic 1 appears on the output of IC2b and for all subsequent inputs a logic 0 is present. At the end of the gating period this output is latched by IC3 forming the lock output.
Frequency comparator circuit - schematic

As this is only valid for one input period a monostable is added to the output to enable, for example, visual monitoring of the output. Either output from IC3 can be used depending on which state is most important. As connected the failure state is indicated.




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