When the lines SDA (Serial DAta) and SDA 'are logical '1', the circuit is at rest with the result that optocouplers IC 1 and IC2 can not convey absolutely no information. But once the SDA line become the 'O', then the LED the IC 1 becomes conductive through the resistor R2. At that time the line SDA 'and it becomes reasonable' O 'because of conductivity of the transistor of IC 1 and D2. This logic state remains on the right side of the channel. After the LED of IC2 can not properly polarized, and therefore unable to transfer back to the left. In this way, ensure that the circuit will never be 'stuck' to logical 'O'. As you noticed, the circuit is symmetrical.
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Thus, if the line SDA 'lead to logical' O ', then the SDA line will also acquire. The lower part of the circuit works like the above, except that here the signal moving is the SCL (Serial CLock). The R 1, A4, A5 and A8 are the usual restraint Elements 3.3 KO which should always be placed on the lines of bus 12C. If the resistors are already co-dedemenes elsewhere in the channel, they can be received by this circuit. The current absorbed by the Bus lines are a little higher than expected due to the presence of LED diodes that optocouplers are parallel with the resistance straps. Nevertheless, the value is still consistent with standard specifications 12C.
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