This circuit design is a class A amplifier employing both ac and de feedback. Bias is stabilized at 15 mA of the collector current using de feedback from the collector. The ac feedback, from collector to base, and in each of the partially bypassed emitter circuits, compensates for the increase in device gain with decreasing frequency, yielding a flat response over a maximum bandwidth. The amplifier shows a nominal 10-dB power gain from 3 MHz to 1.4 GHz.
10Db-gain-amplifier - schematic

With only a minimum matching network used at the amplifier input, the input VSWR remains less than 2.5:1 to approximately 1 GHz, while the output VSWR stays under 2:1. Note that a slight degradation in gain flatness and output VSWR occurs with the addition of C6. A more elaborate network design would probably optimize impedance matching, while maintaining gain flatness.

Leave Comment

characters left:

New Circuits