The circuit works from dc to 50 MHz and will deliver pulses as short as 10 ns. It is driven by a TTL signal through a 740S00 quad Schottky NAND gate, ICA through ICD. Transistor Ql, wired as a common-emitter amplifier, drives transistor Q2, a simple emitter follower. Transistors Q3 and Q4, wired in parallel, also form an emitter follower and drive the output. When Q3 and Q4 are both turned off, transistor Q5 works as a low-impedance sink. Schottky diodes Dl and D2 prevent Ql and Q5 from becoming saturated. To adjust the circuit, potentiometer Rl is set to optimize the output pulse's fall time. Inductor LI, a peaking coil, should be adjusted to improve the rise time to within a permissible 5% overshoot. Likewise, capacitor CI can be varied to control pre-shooting.
Further output pulse shaping is accomplished with the help of capacitor C2. Resistors R2 and R3 ensure a proper 50-ohm impedance at the amplifier's output when the pulse is on or off, respectively.