Integrated circuit Ul (a 555 oscillator/timer) is wired as a conventional pulse generator. The frequency of the pulse generator is controlled by potentiometer Rll. Resistor R2 puts areasonable limit on the highest speed attainable. The output of the pulse generator is fed to the common clock input of U2, a 74C175 quad D-type flip-flop. Each flip-flop is configured so that its Q output is coupled to the D input of the subsequent flip-flop. Information on the D input of.....
In applications where the period of the input pulses is uneven and the divider is required to cover a wide range of frequencies, the non-integer programmable pulse divider shown can be used. The purpose of the D-type flip-flop (IC2) is to synchronize the input signal with the clock pulse. When the clock pulse changes from low to high and the input is high, IC2 output goes high. Subsequently, IC3 resets to zero and starts counting up...
This circuit combines the characteristics of an asynchronous S/R flip-flop and an edge-triggered JK flip-flop. It changes sta..
This circuit traps a single positive pulse from a square-wave train. Following the rising edge of an input command, the pulse-out signal emits a replica of one positive pulse of the clock signal simultane ous with the clock signal"s next rising edge. The 0 input command signal sets the Ql output of flip-flop "----IClA. ..
Circuit uses an astable multivibrator to vary the heads-or-tails condition, and a flip-flop to store the condition given by the multivibrator..
No electrical contact exists between the circuit and the conductor. The 7474 flip-flop is triggered by the output ..
The control of both direction and of proportional motor speed is achieved by rotation of a single potentiometer. The motor driver is an SGS integrated circuit L293 which will drive up to 1 amp in either direction, depending on the logic state of input 1 and input 2 as per table. I/P 1 I/P 2 Function. High Low Motor turns one way. Low High Motor reverses. By applying a variable M/S ratio flip-flop to these inputs, both speed and direction will be controlled. With RV1 in its.....
The circuit"s input op amp triggers the timer, setting its flip-flop and cutting off its discharge transistor so that capacitor C can charge..
Push-pull outputs are used in this transformer-coupled dc-dc regulating converter. Note that the oscillator must be set at twice the desired output frequency as the SGI 524"s internal flip-flop divides the frequency by 2 as it switches the PWM signal from one output to the other..
An input signal drives both SN74 74 D-type flip-flops, which are positive edge-triggered devices. A low-to-high input signal transition triggers tbe A flip-flop, while a high-to-low input signal transition triggers the B flip-flop via tbe SN7404 inverter. Either flip-flop in tbe high state will cause the output to decrease via the SN7402 NOR gate. This in turn disables the opposite flip-flop from going to tbe high state. The flipflop in the high state remains there for.....
The flashing action is provided by a simple astable multivibrator timed to give a flashing rate of about 60 flashes for each lamp per minute. Circuit for positive earth systems uses NPN transistors..
Although this circuit uses a 74HC74, any CMOS variant of this flip-flop will work. IC1A acts as a true/ compleme..
This circuit uses a flip-flop arrangement of Ql and Q2. Normally Ql is conducting heavily. Light on CDS photocell causes Ql bias to decrease, cutting it off, turning on Q2, removing the remaining bias from Q1. ..
This switch uses four CD4013 BE dual flip-flops, an inverter, and an optoisolator to drive a triac. The circuit can switch 25-A ac load current. A standard 4x3 telephone keyboard is used to enter a 6-digit code. In case of a wrong code, a signal is available to activate ah alarm...
The circuit can be used to tell whether or not an input signal is within a certain frequency range. The device consists of three !Cs, a dual monostable multivibrator, and two dual D-type flip-flops. The signal whose frequency is in question is fed to the clock input of one of the flip-flops. The Q output of that flipflop (IC1a) is cross coupled to its data input so that it acts like a divide-by-two counter. The trailing edge of the Q output is used to trigger the one.....
In this mode, the timer functions as a one shot. The external capacitor is initially held discharged by a transistor internal to the timer. Applying a negative trigger pulse to pin 2 sets the flip-flop, driving the output high, and releasing the short circuit across the external capacitor. The voltage across the capacitor increases with the time constant r ~ RAC to 213 V5, where the comparator resets the flip-flop and discharges the external capacitor. The output.....
This approach uses a Hip-Hop, a shift register, and two gates (A). Before the one-shot pulse, the output of the NOR gate is 0. Consequently, the data input of the D-type flip-flop is equivalent to the trigger. When a trigger pulse is present, the flip-flop initiates the one-shot pulse, and the n-stage sliift register controls the pulse width, tw, which is a multiple of the clock`s period (B). The precision of the one- shot, pulse is determined by the clock period, which.....
The monolithic quad operational amplifier provides an inexpensive way to increase display capability of a standard oscilloscope. Binary inputs drive the IC op amp; a dual flip-flop divides the scope"s gate output to obtain channel selection signals. All channels have centering controls for nulling offset voltage..
The oscillator section uses three sections of a 7400 quad NAND gate integrated circuit. The 1-MHz signal from the oscillator is fed into a 7 490 decade counter configured to divide by ten, providing the 100kHz signal. To obtain the 50 and 25kHz outputs, the 100-kHz signal is further divided by 7473 dual J-K flip-flop. The first half of the 74 73 divides the 100-kHz signal by two, yielding the 50 kHz signal. The second half of the 7473 again divides by two, giving the.....
A 555 timer (IC1) generates a 120-Hz signal that is fed to a CD4013BE flip-flop (ICl-a), which divides the input frequency by two to generate a 60-Hz clocking frequency for the FET array (Ql through Q6). ..
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