A shows a typical LTC 1148 surface-mount, application providing 5 V at 2 A from an input voltage of 5.5 V to 13.5 V. The operating efficiency, shown in B, peaks at 97% and exceeds 90% from 10 mA to 2 A with a 10-V input. Ql and Q2 comprise the main switch and synchronous switch, respectively, and inductor current is measured via the voltage drop across the current shunt. /vgENSE is the key component used to set the output, current capability according to the formula/QUT.....
In applications where the period of the input pulses is uneven and the divider is required to cover a wide range of frequencies, the non-integer programmable pulse divider shown can be used. The purpose of the D-type flip-flop (IC2) is to synchronize the input signal with the clock pulse. When the clock pulse changes from low to high and the input is high, IC2 output goes high. Subsequently, IC3 resets to zero and starts counting up...
This circuit combines the characteristics of an asynchronous S/R flip-flop and an edge-triggered JK flip-flop. It changes sta..
When long ranges must be worked with IR light sources, and when high system reliability is required, pulsed-mode operation of the IRis required. Additional reliability of operation is attained by synchronously detecting the photodetector current, as this circuit does. PC-1 is an IR and phototransistor pair which detect the presence of an object blocking the transmission of light from the IR to the phototransistor. Relatively long-distance transmission is obtained by.....
The electromagnetic ring launcher is comprised of.four subcircuits: a clock circuit (built around U5, a 555 oscillator/timer configured for astable operation), a count-down/display circuit (built around U3), a 74190 synchronous up/down counter with BCD outputs that is configured for countdown operation; U4, a ECG8368 BCD-to-7-segment latch/decoder/display driver; and DISP1, a common-cathode seven-segment display), a trigger circuit (comprised of U6), an MOC3010.....
This circuit gives a 3 phase square-wave output for a variable speed motor drive. Operation is straightforward, the 4017 counter is synchronously reset after six clock inputs. The she outputs are combined to give the required waveforms. It is interesting to note that although NOR gates are shown, OR gates will give effectively the same result...
This circuit is a traditional summing amplifier configuration with the addition of the de clamping circuit. The operation is quite simple; each component-synchronization, color burst, picture information, etc.of the composite video signal is applied to its own input terminal of the amplifier. These signals combine algebraically and form the composite signal at the output. ..
The signal from a synchro receiver or a variable resistive cam follower (potentiometer) is boosted by operational amplifier Ul, whose output swing is limited by back-to-back zeners D3 and D4. The signal is then applied to operational amplifiers U2 and U3, which drive the gates of Ql and Q2 respectively. The npn transistor (Q3) is a fast current limiter for the n-channel MTM8N10; a pnp transistor (Q4) performs the same function for the p-channelMTM8P10. Capacitors C3 and C4.....
The scheme presented delivers waveforms from any function generator producing a triangular output and a synchronized TTL square wave. A1 and A2 act as a two-phase current fectifier by inverting the negative voltage appearing at the input of Al. Positive input: Both Al and A2 work as unity gain followers,D1 and D2 being in the off-state. Negative input: Al has a - 2/s gain (D1 off and D2 on), A2 has a + Vi gain and the total voltage transfer is -1 between output and input......
A quad op amp can simultaneously generate four synchronized waveforms. The two comparators (Al and A3) produce square and pulse waves, while the tWo integrators (A2 and A4) give triangular and sawtooth waves. ..
A four thyristor controlled bridge is used for operation in two quadrants of the torque-speed characteristics. In the trigger circuits the usual pulse transformers were replaced by self biased circuits which minimize gate power consumption and increase noise immunity. Electrical isolation is guaranteed by the use of optocouplers. The trigger pulses are generated by the comparison between an error signal, previously processed and amplified, and a line synchronism signal...
This hardware-software combination deletes clocks from the slave until both /iPs synchronize. The firmware..
Two 555s and a quad NAND-gate IC can simulate an electrocardiograph signal and a -y-wave radioisotope signal for applications in nuclear medicine. This circuit synchronizes the radioisotope signal to the EKG signal. You can use the circuit"s outputs to test, for example, microprocessor-based software that calculates the left ventricular ejection fraction before you use the software in clinical applications. IC1. a 555 timer, provides a positive-going pulse train that.....
Both of these converters use CMOS inverters. Figure 105-1A shows a free-running circuit having both the pulse duration and pulse pause dependent on temperature of the diode D8. It can be used where a synchronization between the converter and something else is not required. Figure 105-lB shows a one shot circuit that produces a pulse with its duration dependent of temperature of diode D8. The additional diode D1 should have inverse current low enough to not influence.....
The circuit uses a synchronous-detection scheme to measure low-level resistances. Other low-resis-tance-measuring circui..
The Telephone loll Totalizer—built around two 4 518 dual synchronous up counters, a 74C925 4-digit counter, a 4 58..
This simple circuit generates a dual-speed clock for personal computers. The circuit synchronizes your asynchronous switch inputs with the master clock to provide glitch-free transitions from one clock speed to the other. The dual-speed clock allows some programs to run at the higher clock speed in order to execute more quickly. Other programs- for example, programs that use loops for timing-can still run at the lower speed as necessary. The circuit will work with any.....
Because the CS5501 16-bit-delta-sigma analog-to-digital converter lacks a start convert command, it converts continuously, outputting conversion words to its output register every 1024 cycles of its master clock. However, by incorporating a standard dual J-K flip-flop into the circuit, the ADC can be configured to output a single-conversion word only when it is polled.The CS5501 converter can be operated in its asynchronous communication mode (UART) to transmit one 16-bit.....
Amplifying and limiting of the AM carrier is accomplished by the if gain block providing 55 dB of gain or higher with a limiting of 40 µ\. The limited carrier is then applied to the detector at the carrier ports to provide the desired switching function. The signal is then demodulated by the synchronous AM demodulator (1496) where the carrier frequency is attentuated due to the balanced nature of the device. Care must be taken not to overdrive the signal input so that.....
The circuit uses a track-and-hold amplifier in a closed-loop configuration to clamp the back-porch voltage of a standard video waveform to 0 V. The circuit"s outputs include a clamped composite-video signal and a TTL-level horizontal-blanking pulse. Differential input buffer IC1 and the summing amplifier IC2 isolate the input video signal. Clipper I C4 removes the video signal, leaving only the synchronization information. Differentiator IC5 detects the edges of the.....
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