Based video surveillance system image sensor interface circuit

  
Circuit principle: OV9650 processor interfaces include three parts SCCB interface, data output interface and control interface. SCCB interface to play the role of transfer prov
Based video surveillance system image sensor interface circuit - schematic

ided by the processor internal registers OV9650 initialization parameter, the data line and a clock line SIOD SI-OC, equivalent to the I2C bus SDA and SCL. That is, SC-CB acts I2C bus. OV9650 is I2C bus slave, S3C2440 is the corresponding master. I2 C bus using serial transmission from high to low byte data, each byte transfer is complete, the host controller will set high SDA and released pending confirmation signal sent from the device. OV9650 embedded in a 10-bit A/D converter, corresponding to 10 data outputs D [0: 9]. Format of the output image data may be 10 original RAW, RGB or 8-bit RGB conversion through internal DSP/YCbCr. The choice of CAM IF S3C2440 microprocessor chip unit supports 8-bit YU V/YCbCr format, it takes the OV9650 data interface D [9: 2] data and CAM IF port CAMDAT A [7: 0] Phase connection. The OV9650 XVCLK for receiving an output of 24 MHz CPU operating clock. Frame synchronization signal VSYNC OV9650 internally generated horizontal synchronization signal HREF, the pixel clock signal PCLK other three incoming ARM chip clock signal for controlling image acquisition. Each VSYN C pulse indicates the start of a frame of image data acquisition,




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