Double-ended limit detector

  
Detector uses three sections of an L144 and a CMOS NAND gate to make a very low power voltage monitor. The 1 MO resistors Rl, R2, R3, and R4 translate the bipolar ±10 V swing of the op amps to a 0 to 10 V swing acceptable to the ground-referenced CMOS logic
Double-ended limit detector - schematic

The total power dissipation is 290 µW while in limit and 330 /xW while out of limit.




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