peak detector

The purpose of the circuit is to hold the peak of the input voltage on capacitor Cl, and read the value, V0, at the output of U2. Op amps Ul and U2 are connected as voltage followers. When a signal is applied to Vj, Cl will charge to this same voltage through diode Dl. This positive peak voltage on Cl will maintain V0 at this level until the capacitor is reset (shorted). Of course, higher positive peaks will raise this level while lower power peaks will be ignored. Cl can be reset manually with a switch, or electronically with an FET that is normally off.

The capacitor specified for Cl should have low leakage and low dielectric absorption. Diode Dl should also have low leakage. Peak values of negative polarity signals may be detected by reversing Dl.

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sarath   Oct 4, 2017

how can i detect a signal of 1.2v peak to peak and hold it and it should detect both neagtive and positive half cycle at 1.2v peakto peak

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