Serial PCI Express Bus

The PCI Express (PCIe) bus defines the electrical, topology, and protocol aspects of a point-to-point serial interface over copper wire or optical fiber. In addition to the Physical Layer, the PCI Express specification also covers the Transaction Layer and Data Link Layer. The Physical Layer corresponds to Layer 1, while the Data Link Layer corresponds to Layer 2 of the OSI protocol model. PCI Express is the latest serial bus addition to the PCI series of specifications. However, the electrical and mechanical interface for PCI Express is not compatible with the PCI bus interface. This serial bus utilizes two low-voltage differential signaling (LVDS) pairs, operating at 2.5 Gb/s in each direction (one transmit and one receive pair). A PCI Express link consists of these two unidirectional differential pairs, each functioning at 2.5 Gbps, resulting in an overall throughput of 5 Gbps (before accounting for overhead). PCI Express employs 8B/10B encoding, where each 8-bit byte is converted into a 10-bit character to balance the number of 1's and 0's transmitted, with the encoded signal containing an embedded clock. PCI Express supports various bus widths (1x, 2x, 4x, 8x, 12x, 16x, and 32x), with a bandwidth of 2.5 Gigabits/second per lane in each direction. The 8B/10B encoding results in a raw data transfer rate of 250 MBps per lane. The throughput reduction is accounted for in the protocol specifications. Revision 3.0 (Gen 3), released in 2010, increases the speed to 8 GT/s and modifies the encoding to 128b/130b to minimize overhead. The new bandwidth rises from 4 Gb/s (Gen 2) to 7.99 Gb/s due to reduced overhead and bit time. The basic LVDS interface comprises a single differential link that can operate in one or both directions, necessitating a termination resistor at the far (receiver) end. The nominal resistor value is typically 100 ohms, but this may vary based on the cable or printed wiring board (PWB) trace impedance. LVDS is a scalable bus, allowing for either a single unidirectional link or multiple links. The PCIe specification permits a maximum trace length of 20 inches, although PCIe version 2.0 supports cables up to 10 meters in length at 2.5 Gb/s. The PCI Express bus began appearing on motherboards in 2004 as an addition (utilizing a new connector) to the PCI interface, coexisting with and surpassing parallel PCI, similar to how PCI replaced the ISA bus. A common PCIe implementation features two 1x PCI Express slots for expansion boards and one 16x PCIe slot, which replaces the AGP slot, in addition to several standard parallel (classic) PCI slots (three to four connectors). Given the extensive deployment of PCI boards, it may take time for PCI expansion slots to become obsolete, though the smaller size of the PCIe 1x connector may accelerate this process. The 1x PCIe slots support a bandwidth of 5 Gbps, while the 16x PCIe slot can support up to 80 Gbps. Some motherboard manufacturers incorrectly use the term PCI-E to denote PCI Express card slots, whereas the correct term is PCIe. PCI Express is not compatible with the standard PCI bus, as the connectors, signal voltage levels, and signal formats differ from those of PCI. PCI Express cards have dimensions similar to standard PCI cards, but the main physical distinction between the two bus formats lies in the connectors, with PCI Express available in both standard and low-profile form factors. Some software designed for the PCI bus may be compatible with the PCIe bus. PCI Express was initially developed by Intel's Arapahoe working group, originally referred to as 3GIO (third-generation input/output). The specification has since been transferred to the PCI Special Interest Group (PCI-SIG).

The PCI Express (PCIe) architecture represents a significant advancement over previous bus technologies, providing a high-speed, point-to-point connection that enhances data transfer rates and overall system performance. The design employs a layered approach, integrating multiple layers of functionality, including the Physical Layer, Data Link Layer, and Transaction Layer, which work in conjunction to facilitate efficient communication between devices.

The Physical Layer is responsible for the electrical and mechanical specifications of the interface, defining the characteristics of the LVDS signaling used for data transmission. The use of low-voltage differential signaling enables high data rates while minimizing electromagnetic interference, making PCIe suitable for high-performance computing environments.

The architecture supports various lane configurations, allowing for scalability based on application requirements. Each lane operates independently, enabling simultaneous data transmission and reception, which is particularly beneficial in multi-device scenarios. The encoding scheme employed, specifically 8B/10B and its successor 128b/130b in later revisions, ensures reliable data integrity and synchronization, further enhancing the protocol's robustness.

PCIe's compatibility with a range of devices, including graphics cards, network interfaces, and storage controllers, has made it the preferred choice for modern computer systems. The introduction of different slot sizes (1x, 4x, 8x, 16x) allows for versatility in system design, accommodating various performance needs without compromising on space or efficiency.

The transition from PCI to PCIe has been marked by a gradual phasing out of legacy PCI slots, as manufacturers increasingly adopt PCIe technology in their designs. This shift is driven by the need for higher bandwidth and lower latency in data transfer, which are critical factors in contemporary computing applications.

Overall, PCI Express is a cornerstone technology in modern electronics, enabling high-speed data communication and supporting the evolving demands of computing and networking technologies. Its ongoing development and refinement ensure that it remains at the forefront of interface technology, adapting to the needs of future applications.The PCI Express [PCIe] bus defines the Electrical, topology and protocol for the physical layer of a point to point serial interface over copper wire or optical fiber. In addition to the Physical Layer, the PCI Express specification also covers the Transaction Layer and Data Link Layer.

The Physical Layer resides with Layer 1, and the Data Link La yer resides with Layer 2 of the OSI protocol model. PCI Express is the new serial bus addition to the PCI series of specifications. How ever the electrical and mechanical interface for PCI Express is not compatible with the PCI bus interface. This is a serial bus which uses two low-voltage differential LVDS pairs, at 2. 5Gb/s in each direction [one transmit, and one receive pair]. A PCI Express link is comprised of these two unidirectional differential pairs each operating at 2. 5Gbps to achieve a basic over all throughput of 5Gbps [before accounting for over-head]. PCI Express uses 8B/10B encoding [each 8 bit byte is translated into a 10 bit character in order to equalize the numbers of 1`s and 0`s sent, and the encoded signal contains an embedded clock].

PCI Express supports 1x [2. 5Gbps], 2x, 4x, 8x, 12x, 16x, and 32x bus widths [transmit / receive pairs]; 2. 5Gigabits/second per Lane per Direction. The 8B/10B changes the data transfer numbers to 250MBps per lane, raw data [B= Bytes, b=Bits]. The reduction in throughput is accounted for under the protocol section. Revision 3. 0 (Gen 3) due out in 2010 increases the speed to 8GT/s and changes the encoding to 128b/130b to reduce the over head. The new bandwidth will increase from 4Gb/s (Gen 2) to 7. 99Gb/s both from over head reduction and bit time reductions. Note; Giga-Transfers per Second (GT/s) The basic LVDS interface is a single differential link in either one or both directions.

Each link requires a termination resistor at the far [receiver] end. The nominal resistor values used is 100 ohms, but would depend on the cable or PWB trace impedance used. LVDS is a scalable bus; one uni-directional link or multiple links may be used. The LVDS graphic above indicates a 1-meter length, but the PCIe specification only allows a 20 inch trace.

Refer to the LVDS page for additional information. The new PCIe version 2. 0 supports cables up to 10 meters in length running at 2. 5 Gb/s. The PCI Express bus started showing up on Mother Boards in 2004 as an addition (using a new connector) to the PCI interface, and will coexist and out-pace parallel PCI at the rate PCI took over from the ISA bus. One common PCIe implementation seems to have two 1x PCI Express slots [for expansion boards] and one 16x PCIe slot [used to replace the AGP slot], then some number of standard parallel (classic) PCI slots [3 to 4 connectors].

Because of the large number of PCI boards fielded it may be some time before the PCI expansion slots disappear from mother-boards, but may disappear faster because the PCIe 1x connector is so much smaller then the PCI connector. The 1x PCIe slots will support a bandwidth of 5Gbps, and the 16x PCIe slot will support 80Gbps. Throughput is discussed below. I see some Mother Board manufacturers using the term PCI-E to represent PCI Express card slots, this is an incorrect usage [PCIe].

PCI Express is not compatible with the standard PCI bus. The PCI Express connectors, signal voltage levels, and signal format are different then with PCI. The physical size of PCI Express cards have the same dimensions as standard PCI cards. The main physical difference between the two bus formats lay with the connectors. PCI Express comes as either standard or low-profile form factors. Additional Notes: Some software written for the PCI bus may be compatible with the PCIe bus. PCI Express was originally developed at Intel by the Arapahoe working group. Later called 3GIO, "third-generation input/output". Now that the spec has been transferred to the PCI Special Interest Group (PCI-SIG) it w 🔗 External reference