Digital CMOS Circuits Tutorial (page 2)

  

 

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⚛ Introduction To CMOS Technology ⚛ Logic CMOS Gates ⚛ Schmitt Trigger CMOS Circuit ⚛ Logic CMOS Families
⚛ The MOSFET Transistor ⚛ Static Logic CMOS Structures ⚛ Inputs Compatible with TTL levels ⚛ Conventional Logic CMOS Families
⚛ Operation of MOSFET Transistor ⚛ Dynamic CMOS Logic Structures ⚛ CMOS Output Levels ⚛ Low Voltage CMOS Logic Families
⚛ The MOSFET Transistor as a Switch ⚛ Alternative Logic Structures ⚛ CMOS Driving Capability ⚛ Inputs Tolerant to Overvoltages
⚛ Basic Structures of MOSFET Transistor ⚛ Input-Output CMOS Circuits ⚛ Other CMOS Output Structures ⚛ Evolution of CMOS Technology
⚛ MOSFET Propagation Gate ⚛ CMOS input levels ⚛ Power Consumption of CMOS Circuits  
⚛ Pull Up and Pull Down in CMOS ⚛ Non-Driven Inputs and Slow Transition Inputs ⚛ Static Power Consumption  
⚛ The CMOS Inverter   ⚛ Dynamic Power Consumption  
    ⚛ Charging of External Capacities  
    ⚛ Charging of Internal Capacities  
    ⚛ Short-Circuit Current  
    ⚛ Total Power Consumption  
    ⚛ Maximum Power Consumption  

 

 

 

Logic CMOS Gates

This section introduces various techniques for designing digital circuits with CMOS technology. The most common method of implementing logic functions is an extension of the basic circuit of the inverter, which was presented in the previous section. The operation of these circuits is static, producing stable output levels as long as their inputs remain constant.

CMOS static logic circuits are robust in operation, have minimal power consumption, are easily designed and built and are the most common type of CMOS digital circuits.

In addition to CMOS static circuits, there are also alternative logic circuit design methods, which are preferred only when there are special space or performance requirements.

 

 

Static Logic CMOS Structures

The implementation of logic functions through CMOS static circuits is an extension of the inverter circuit as presented. Each logic function is implemented through two complementary pullup and pulldown motions, as shown in Figure 3-12 (a).

Static logic CMOS structures

 

Figure 3-12

 

The pulldown, consisting of NMOS transistors, connects the logic output Y to the low level (GND). The output function is implemented by connecting NMOS transistors in series, in parallel or in a combination of the two modes:

  • A) When two NMOS are connected in series, they form a conductive path only when both of their gates are at the high logic level. The conduction function (not voltage) represents the logic-AND (AND).
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  • B) When two NMOS are connected in parallel, there is a conductive path when even one gate of a transistor is at a high logic level. The conduction function represents the logic-H (OR).

By combining NMOS transistors in series and at the same time the desired conduction function F is realized. When there is a conductive path between Y and GND, then the output is in the low logic state.

The opposite happens to the potentiometer: consisting of a PMOS transistor, connects the output to the high logic level (VDD) when there is a conductive path between Y and VDD. The PMOS transistors are connected in addition to the NMOS (ie, the serial connection is parallel and inverse) and implement the conduction function F.

CMOS logic structures only implement inverted functions (NAND, NOR, XNOR) and use 2N transistors for N inputs. To receive non-inverted functions, an additional inverter must be connected to the output. Figure 3-12 (b) depicts the implementation of a two-input NAND logic gate.

As in the case of the CMOS inverter, the logic circuits presented in this paragraph have static characteristics: in steady state (when the inputs are constant) the output Y is connected to either VDD or GND and continuously outputs the function F it implements. Logic circuit operation is independent of the sizes of the NMOS and PMOS transistors and is not affected by small manufacturing deviations.

CMOS static logic circuits show practically zero power consumption at steady state, because when the inputs and outputs are stable, there is no conductive path between the supply and ground, hence neither the current flowing through the circuit (with the exception of a minimal current Leakage of the transistors into a cut, but which is so small that it can be ignored). Power consumption is dynamic due to the charging-discharge capacity current and the short-circuit current, which occur when the output status changes.

CMOS static circuits have some drawbacks, especially when the fan-in input is large: the 2N transistors, which are needed for logic N input circuits, require a large surface to be built.

Also, the total output capacity of the logic circuit, which is composed of the drain capacities of all the transistors connected to the Y output, is also great. The increased output capacity requires a sufficient current load for charging-discharging during the change state And implies a reduced speed of the logic circuit.

Finally, when a large number of transistors is connected in series, then the resistance presenting the total of the transistors in the current flow is multiples of the RON of one. Therefore, the current for charging-discharge of the capacitances of the logic circuit flows more difficult, increasing the propagation delay of the circuit.

Regarding the effect of the number of similar logic circuits connected to the fan-out output, each of the driven circuits adds to the output the two transistor gatepower capacities: a PMOS and an NMOS.

The disadvantages mentioned above only affect performance rather than the functionality of a static CMOS circuit. For this reason, the CMOS static logic circuits make up the majority of the CMOS circuitry, due to their ease of construction, low power consumption and robust operation.

 

 

Dynamic CMOS Logic Structures

The basic idea behind the CMOS dynamic circuits is illustrated in Figure 3-13. In relation to a static CMOS logic circuit, the pullup segment has been removed here and the output is driven only by the NMOS transistor section. Additionally, two transistors (NMOS and PMOS), driven by a clock waveform (CLK), enclose the logic circuit.

Dynamic logic CMOS structures

 

Figure 3-13

 

Pull-up and the output is driven only by the NMOS transistor section. Additionally, two transistors (NMOS and PMOS), driven by a clock waveform (CLK), enclose the logic circuit.

Circuit operation is accomplished in two phases:

 

  • A) in the precharge phase, when the CLK is at a low logic level, the parasitic capacities of the Y output are charged via PMOS to a VDD voltage. The NMOS transistor does not go.
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  • B) in the assessment phase, CLK is at a high level, the PMOS at cut-off, and the NMOS conducts. If there is a conductive path in the pulldown segment, then the parasitic Y capacity is discharged through the ground. Otherwise Y remains at a high level.
  •  

Pre-charging and computation functions must be performed continuously, because the parasitic Y capacity is discharged over time through leakage currents. For this reason, logic circuits similar to Figure 3-13 are called dynamically.

The advantages achieved with the use of CMOS dynamic circuits are the following:

 

  • A) With the removal of the pullup section of the PMOS, space saving is achieved. For N input circuit N + 2 transistors are required.
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  • B) Parasitic capacities are smaller because of the reduced number of transistors. This makes the logic circuit faster.
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  • C) Status change rate is two to three times greater than that of static CMOS. NMOS transistors are faster than PMOS and drive as soon as gate voltage exceeds VT.
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Power consumption is greater than CMOS static circuits, although there is no short circuit current. The increase in consumption is due to the fact that the dynamic circuit has a constant state switching activity (due to the pre-charge cycles) even when the inputs do not change state.

Dynamic CMOS logic circuits, though faster, have difficulty in designing them and are therefore only used in special requirements circuits. Some of the problems of dynamic circuits are:

 

  • A) Maintaining the load on the parasitic output capacity is difficult due to leakage currents. Also, the load tends to be shared between the nodes of the pulldown segment, thus degrading the high output signal.
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  • B) The dynamic circuit requires the production of a fixed CLK signal.
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  • C) Output Y, when there is no conductive path to the ground during the calculation phase, is not driven either by VDD or by GND. During this time, the output signal is vulnerable to interference from neighboring signals.
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  • D) In ​​the calculation phase, the inputs of a potential circuit must perform a single switch from low to high. If for any reason an input is incorrectly found at a high level, it is likely that the Y capacity will be discharged without being able to return to a high level even if the input returns to a low level.
  •  

By adding an inverter to the Y output, it is ensured that for input signals, which make a single switch from low to high, then the outputs show the same type of transition. So many dynamic logic steps can connect one to the other's output, implementing the so-called domino logic.

 

 

Alternative Logic Structures

In addition to static and dynamic CMOS logic structures, there are several alternative structures, two of which appear in Figure 3-14.

Alternative CMOS logic structures

 

Figure 3-14

 

The pseudo-NMOS logic (Figure 3-14a) uses only the NMOS (pulldown) segment and in the pullup section it uses a PMOS transistor that continuously runs as a single load. For N inputs, N+1 transistors are required. In early technologies with NMOS only, the PMOS position occupied an NMOS dilution transistor. Thus the circuit of Figure 3- 14 (a) was named "pseudo-NMOS".

In the pseudo-NMOS circuits the PMOS transistor is permanently in process. When there is no conductive path to the ground in the NMOS section, the output is at a high logic level (VDD). But when the NMOS section is running, the output voltage is determined by the driving capability and the "competition" between PMOS and NMOS.

The low output level is greater than GND, and the relative pullup and pulldown transistor ratios are decisive for the ratio ratio logic. Unlike the logic structures presented in previous paragraphs, the sizes of the transistors determine not only performance but also the functionality of the circuit.

The pseudo-NMOS logic is rarely used today because it consumes static power. When the output is low, a significant amount of current flows continuously between power supply and ground, via the PMOS and the pulldown transistor. Significant power consumption makes the pseudo-NMOS logic inappropriate for great integration.

The logic with propagation gates (Figure 3-14b) is a completely different logic structure. The general idea is to select (multiplex) a set of input signals, using the terms of certain selection signals. PMOS transistors are used to pass high logic level and NMOS for low.

Logic structures with propagation gates are implemented in a simple design and do not exhibit static power consumption. On the other hand, the outputs of these circuits are not connected to VDD or GND except through the inputs via a RC network of the transistors, degrading the signal quality.

 

 

Input-Output CMOS Circuits

The I/O devices of integrated CMOS circuits, as well as all digital circuits, interconnect the internal logic circuits with the "outside world" and require special attention in their design. These devices have to cope with voltages and currents much larger than the internal circuits of the integrated circuit. Figure 3-15 illustrates standard CMOS input-output devices.

Input Output Connections

 

Figure 3-15

 

Both the input stages and the output stages consist of a CMOS inverter. In order to protect the MOSFET transistors from surges and sudden current flow, devices (diodes, resistors, etc., in fact more complex than in Fig. 3-15) are added, which are realized at the silicon-metal levels.

In the input stages the main purpose of the protection is to remove the positive and negative surges from the sensitive gates of the transistors. At the outputs, the diodes prevent the excessive current from passing through the drain-source of the output transistors. The passages in the output stages (Figure 3- 15b) are parasitically (but desirable) between the drain and substrate of the MOSFETs, although additional protection diodes are usually added.

The main threat to a CMOS integrated circuit is electrostatic discharge (ESD): when two bodies with different static electric charges approach each other, a spark is created by exchanging static charges between the two bodies. In an integrated circuit, this can happen when a pin comes in contact with the charged human body (3-5KV) or an assembly machine.

During electrostatic discharge, voltages from 3KV to 30KV are applied to the terminals of the integrated circuit for a few ns while the current flowing momentarily to the terminals is some A. Without the protection devices in the input / output stages of the CMOS circuits, MOSFET transistors are usually destroyed, either by gate oxide perforation, or by overheating of source drain-source contacts.

The sharp current flow can also cause a phenomenon called latchup: due to the way MOSFET is made, parasitic bipolar transistors are formed within the silicon levels. These transistors, when they are "triggered" by an abnormal current flow, are stabilized in a conductive state by virtually shortening the supply voltage to the ground and ultimately destroying the integrated circuit.

Modern CMOS circuits have efficient protection devices and are designed to minimize side effects such as electrostatic discharge and latchup. An additional effect of the protection devices is to limit the signal level to the input or output in normal operation by a diode drop over the supply voltages.

 

 

CMOS input levels

Each input terminal of an integrated CMOS circuit is connected to the isolated gates of the NMOS and PMOS transistors. Due to the isolated transistor gates, input impedance is very high (typically 1012). Thus, when the logic input level remains constant, the current flowing through the inputs is practically zero (of the nA class, with a maximum value of 1μA).

In CMOS circuits, the most important parameter that characterizes each input is its capacity. Input capacity determines the required electrical charge to be moved to change the logic state. Input capacity is comprised of the capacities of the input stage, MOSFET transistors, protection circuits, and packing capacity from the terminal to the silicon surface. Typical values ​​for the input capacity are 3-5pF, while the maximum values ​​given by manufacturers are between 10 and 15pF.

 

 

Non-Driven Inputs and Slow Transition Inputs

The input stages of a CMOS circuit must always be driven by a strong signal to the high (VDD) or low (GND) logic level. In other words, a CMOS input is never allowed to be left unattached in the air (floating input). The isolated inputs of the CMOS circuits, if left unconnected, can be found in the threshold area for an unlimited period of time. In this area, the PMOS and NMOS transistors of the input stage simultaneously drive a strong short-circuit current. Under normal conditions (when an input changes level), this current does not affect the operation of the integrated circuit. However, when the input is in the range of the threshold voltage over a prolonged period, the short-circuit current causes overheating of the integrated circuit. Also, when the input signal is constantly in the threshold range, the logic outputs tend to oscillate continuously between the two logic levels, which can also damage the integrated circuit.

Bus hold circuit

 

Figure 3-16

 

For the above reasons, unused inputs of a CMOS circuit must always be connected to either the VDD or the ground. In the case of data busses, where one output transmits signals to multiple receivers, it must be ensured that at any time the bus is driven by one output. Otherwise, there is a risk that the channel (and all the entrances connected to it) will be found "in the air". Newer CMOS integrated circuits, which are intended for channel interconnection, have an additional bus-hold at their inputs (Figure 3-16). This circuit consists of a "weak" inverter (NMOS and PMOS pair), which feeds the input with the last valid signal as long as the input is "in the air".

For reasons similar to those mentioned earlier, modern high speed CMOS integrated circuits are sensitive to slow-cathode inputs. Slow transition of one input from one logic level to another may cause logic errors or oscillations at the output. This is due to the noise caused by fast state changes, typical in modern circuits, on power lines.

Feed lines (mainly ground) are used as reference voltages to determine whether an input is at a low or high logic level. The noise momentarily shifts the threshold voltage and so a very slowly changing input can easily be found in the opposite logic state. In the worst-case, when the noise is too strong, the slow input signal can be repeatedly over and below the threshold voltage, causing oscillations at the output.

Manufacturers of CMOS digital circuits set a maximum transition time of input signals (tt to ns) (for older integrated circuits) or a maximum transition rate (Δt / Δv in ns/V) (for newer circuits).

 

 

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