Digital CMOS Circuits Tutorial (page 3)
|Page 1||Page 2||At this page (3)||Page 4|
|⚛ Introduction To CMOS Technology||⚛ Logic CMOS Gates||⚛ Schmitt Trigger CMOS Circuit||⚛ Logic CMOS Families|
|⚛ The MOSFET Transistor||⚛ Static Logic CMOS Structures||⚛ Inputs Compatible with TTL levels||⚛ Conventional Logic CMOS Families|
|⚛ Operation of MOSFET Transistor||⚛ Dynamic CMOS Logic Structures||⚛ CMOS Output Levels||⚛ Low Voltage CMOS Logic Families|
|⚛ The MOSFET Transistor as a Switch||⚛ Alternative Logic Structures||⚛ CMOS Driving Capability||⚛ Inputs Tolerant to Overvoltages|
|⚛ Basic Structures of MOSFET Transistor||⚛ Input-Output CMOS Circuits||⚛ Other CMOS Output Structures||⚛ Evolution of CMOS Technology|
|⚛ MOSFET Propagation Gate||⚛ CMOS input levels||⚛ Power Consumption of CMOS Circuits|
|⚛ Pull Up and Pull Down in CMOS||⚛ Non-Driven Inputs and Slow Transition Inputs||⚛ Static Power Consumption|
|⚛ The CMOS Inverter||⚛ Dynamic Power Consumption|
|⚛ Charging of External Capacities|
|⚛ Charging of Internal Capacities|
|⚛ Short-Circuit Current|
|⚛ Total Power Consumption|
|⚛ Maximum Power Consumption|
Schmitt Trigger CMOS Circuit
A Schmitt trigger CMOS circuit (Figure 3-17a) can be used to convert a slowly ascending or descending signal.
Assuming that the Vin of figure 3-17 (a) is equal to "0", then P1, P2 proceed while N1, N2 are cut off. Vout output equals VDD. Transistor N3 is connected as a source follower and transfers a part of Vout to point A between the two NMOS transistors. When the Vin voltage begins to shift to "1", it first powers the transistor N1, once Vin exceeds the VT voltage (NMOS). The voltage at point A is determined by the voltage divider forming N1 and N3. When Vin exceeds a certain voltage VT + ( > VDD / 2 ) then N2 also starts to lead by driving the Vout output to GND. At the same time P3 is driving, transferring the low output between the PMOS and leading P2 to cut off. The transition ends with P1 being driven to a cut.
The transition from "1" to "0" is done in the same way, except that the output change occurs when the input equals VT - ( < VDD / 2 ). The difference of the two transition thresholds is also called "hysteresis" (Figure 3-17b) and ensures that a slow or noisy signal will not oscillate around a single threshold voltage, as is the case with normal CMOS inputs.
Inputs Compatible with TTL levels
An integrated circuit with reasonable TTL output levels (VOH(min) ≈ 2.4V) can not directly lead a CMOS input (VIH(min) ≈ 70% VDD, ie 3.5V for VDD = 5V). For compatibility reasons, CMOS inputs with a different size ratio for the input stage inverter transistors are manufactured. The NMOS transistor is magnified about seven times compared to PMOS, shifting the inverter's threshold voltage from VDD / 2 to 1.5V (VDD = 5V), similar to the threshold voltage of the TTL circuits. This change allows you to drive the input at TTL levels. It should be noted, however, that with these levels (VOL = 0.4V, VOH = 2.4V) the two transistors partly run simultaneously, increasing power consumption.
CMOS Output Levels
The simple electrical equivalent of a CMOS output stage is illustrated in Figure 3-18. Depending on the logic output level, one of the two MOSFET transistors drives (in the figure they are represented by switches), connecting the output either with the VDD or with the ground. Through the corresponding equivalent RON resistance current flows to charge the load capacities, which is connected to the output of the circuit.
In integrated CMOS circuits, the drive's output capacity at the two logic levels (i.e., the maximum amount of current supplied to the high or lowered level) is symmetrically equal in design. The output stage transistors have a high gain factor k and a very low equivalent RON resistance (100Ω or less), allowing for increased power supply to the driven load. The supplied power increases as the supply voltage increases, decreasing as the temperature increases (-0.3%/°C for standard CMOS circuits).
When the output does not lead any load, then the high output voltage (VOH) equals VDD. In the same situation, the low output voltage (VOL) is equal to ground. These unladen trends are of no practical significance. For this reason, manufacturers list the output levels (VOH(min), VOL(max)) with a non-zero output current (IOH(max) and IOL(max) respectively).
From these values it is possible to calculate the equivalent RON resistance for the two logic levels (The RON resistance calculation is approximated. In fact, RON has a dynamic value, depending on the output voltage):
RON(H) = [VDD - VOH(min)] / IOH
RON(L) = [GND - VOL(max)] / IOL
CMOS Driving Capability
This section examines the fan-out of a CMOS output when it drives similar circuits (with CMOS inputs). In stable logic state, CMOS inputs are not leaking. In theory, a CMOS output could lead to an unlimited number of CMOS inputs. In fact, however, the driving ability in this case depends on the transient characteristics, ie the loads that move when changing the logic level of the output.
As shown in Figure 3-18 of the previous paragraph, for the transition of the output from one logic level to the other, a quantity of current is required to charge / discharge the load capacity CL. The output does not momentarily go to the desired level. Instead, the transition is gradual and is determined by the time constant of the simple RC circuit, which is formed by the RON of the conductor transistor and the CL capacity. The time required to move from one level to another (from 10% to 90%) is equal to:
T10% - 90% = 2.2RONCL
Where RON is calculated as in the previous paragraph for the worst case (usually RON(H) is the highest value), while CL is equal to the sum of the capacities of the gates (n * Ci) plus the additional capacity of the interconnection line.
Knowing the electrical characteristics and time constraints of each application, the above equation can be resolved to n, defining the maximum fan-out of the specific output. Even in the theoretical case where there are no time constraints on implementation, the maximum transition time limit for CMOS inputs applies. Using the maximum transition time (from manufacturer's datasheets) to the equation, the theoretical maximum fan-out for that CMOS output is calculated.
Other CMOS Output Structures
The classic CMOS output stage, which was previously presented, consists of a combination of pullup and pulldown of the output voltage. Apart from this figure, CMOS outputs of different morphology are also used, which are used in special cases of interconnection (Figure 3-19):
An output of three states can be constructed as in Figures 3-19 (a) and 3-19 (b), by isolating the output terminal under the control of an enable signal. The isolated output terminal is not driven to VDD or GND, but has an output capacity.
Figure 3-19 (c) depicts an output stage without the PMOS transistor to raise the voltage. Here is a pullup external pull to the VDD to create the high logic level. This device is called an open-drain output in analogy with the open collector outputs of bipolar transistors and is used to implement wired-AND connections.
Power Consumption of CMOS Circuits
The total power consumption of an integrated CMOS circuit consists of two components:
- A) Static power consumption in quiescent power, which occurs in the CMOS integrated circuit when the inputs and outputs do not change state.
- B) Dynamic power consumption for charging / discharging internal and external capacities during the cost transitions between the two logic states.
The following paragraphs analyze the above components of power consumption and their specific characteristics are listed.
Static Power Consumption
The static power consumption of an integrated CMOS circuit in a resting state is mainly due to the leakage currents between the reverse polarized diffusion regions and the substrate. On quiescent CMOS circuits there is no conductive path between VDD and GND. The total leakage current, commonly referred to as ICC (Manufacturers datasheets use the terms ICC and VCC equally in place of IDD and VDD), is very small in size: 10-40μA for a standard CMOS logic circuit or up to 200μA for a medium integration circuit (MSI). Static PS power consumption equals the product of the leakage current with the VCC supply voltage (ICC and VCC terms in the IDD and VDD equally apply to manufacturers' datasheets):
PS = ICC x VCC
Because of the small size of the ICC, the static power consumption is correspondingly very low: in medium integration circuits the typical value of static power consumption is 0.1-0.2 μW / gate. This makes CMOS circuits ideal for low power applications, compared to bipolar transistor circuits where considerable power is consumed at rest.
As can be seen, the ICC leakage current is proportional to the complexity of the integrated circuit. Also, the ICC rises the higher the temperature. Table 3-2 below lists typical ICC values for different types of integrated HCMOS at certain ambient temperatures (TA):
average completion circuit
Table 3-2: HCMOS loop leakage current, VCC = 6V
Dynamic Power Consumption
Dynamic consumption is the main part of the power consumption of an integrated CMOS circuit. Dynamic power consumption occurs when the circuit passes from one reasonable level to another due to:
- A) the current required for charging / discharging the external capacities (of the driven circuit) when changing the status of the exits,
- B) the corresponding current required for charging / discharging the internal nodes of the CMOS circuit itself; and
- C) the short-circuit current, which occurs momentarily when switching through the PMOS and NMOS transistors.
Generally, the current displayed during the status switching depends on the operating frequency and the up/down times of the input signals.
Charging of External Capacities
When the logic status of a CMOS output is changed (Figure 3-18), a certain amount of current is required to charge or discharge the external capacitance CL, which represents the capacities of the driven circuits. The corresponding energy is consumed at the equivalent RON resistance of the output stage.
The energy required for a full charging-discharge cycle is equal to E = CL · VCC2 and respectively the power consumption at the switching frequency fo is P = CL · VCC2 · fo.
In the case of an integrated CMOS circuit with N outputs connected to a CL load each, with a single output frequency fo, the power used for charging/discharging the external capacities according to the above equals:
PL = CL · VCC2 · fo · N
While each output is connected to a different load and changes status with a different frequency:
PL = Σ (CL(i) · fo(i)) · VCC2
It is obvious that in order to achieve low power consumption some of the terms of the above equations, that is the capacitive load, the switching frequency or the supply voltage, should be reduced.
Charging of internal capacities
Each CMOS integrated circuit spends energy when switching the state to charging or discharging its internal capacities. For each internal node i with a capacity of Ci, the consumed power is given by the relation Pi = Ci · VCC2 · f, where f is the operating frequency of the node.
In theory, the sizes of each node could be summed to find the total internally consumed power. However, this calculation can not be implemented by the users of the integrated circuit. For this reason, manufacturers provide the data sheets with an equivalent CPD power consumption capacity, from which the internal power consumption PT is calculated as follows:
PT = CPD · VCC2 · f
For any operating frequency f of the circuit. The concept of "operating frequency" is different for each type of circuit and should be carefully calculated for a more accurate approximation of actual power consumption:
- A) For simple combinational circuits (gates) it can be considered equal to the frequency of switching of output fo.
- B) For buffers equals the input frequency of the signal fi (for each of the input signals). If the isolation circuit has a clock, a better approximation is given by the relation f = fCLK / 2 + Ni · fi, where fCLK is the clock frequency, f is the input frequency and Ni is the number of inputs that change at frequency fi.
- C) For flip-flops, latches can be considered equal to the frequency of the fCLK clock.
In any case, manufacturers give specific instructions for using the CPD, depending on the functionality of the integrated circuit. Usually CPD is given per gate and not the whole circuit.
The CPD is calculated by the manufacturer of the integrated circuit by measuring the current consumed without external load for various combinations of inputs and operating frequencies in relation to the supply voltage.
The short-circuit current occurs when changing the logic state due to instantaneous simultaneous conduction of the PMOS and NMOS transistors of the various stages of an integrated CMOS circuit. The short-circuit current and the corresponding power consumption are proportional to the supply voltage, operating frequency and up/down times of the input signal.
Although in this case the power consumed is proportional to the VCC and not the VCC2, the manufacturers incorporate the effect of the short-circuit current on the CPD. Thus, the PT calculation of the previous paragraph also contains the power consumption due to the short-circuit current.
This approach is accurate for normal up / down times of input signals. Otherwise, the power consumption due to the short-circuit current is significant and is not covered by the CPD calculation.
Total Power Consumption
Based on the data of the preceding paragraphs, the total power consumption P of an integrated CMOS circuit is equal to:
P = PS + PL + PT = ICC · VCC + Σ (CL(i) · fo(i)) · VCC2 + CPD · VCC2 · f
The determining factor for total power consumption is linear dependence on the operating frequency of the integrated circuit. As the operating frequency increases, dynamic power consumption in a CMOS circuit becomes critical. From a certain frequency beyond, the total power supply and total power consumption of a CMOS circuit approximate the sizes of a circuit with bipolar transistors (Figure 3-20). However, CMOS circuits retain the advantage of low power consumption for the following reasons:
- A) In a composite integrated circuit, not all internal nodes operate at the maximum operating frequency. Thus, CMOS circuits show reduced power consumption at lower frequency nodes, unlike bipolar circuits, where power consumption remains high for these nodes. The economy in power consumption can be optimized with proper low-speed architecture design.
- B) The reduction of the supply voltage can bring significant benefits to power consumption, since the power is dependent on the VCC square. Modern CMOS integrated circuits operate at less than 5V supply voltages and achieve low overall power consumption at high operating frequencies.
Maximum Power Consumption
The maximum power consumption of an integrated circuit is determined by the maximum junction temperature (TJ) of the temperature, i.e. internally to the integrated circuit. The contact temperature is equal to the ambient temperature TA, incremented depending on the power consumption P:
TJ = TA + θJA x P
Where θJA is called the thermal resistance coefficient (οC/W) and depends on the packaging of the integrated circuit. This factor is given by the manufacturer as well as TJMAX and TA. Thus, it is possible to determine the maximum allowable power consumption (without cooling) of the circuit:
Pmax = (TJMAX-TA) / θJA