Digital CMOS Circuits Tutorial (page 4)

  

 

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⚛ Introduction To CMOS Technology ⚛ Logic CMOS Gates ⚛ Schmitt Trigger CMOS Circuit ⚛ Logic CMOS Families
⚛ The MOSFET Transistor ⚛ Static Logic CMOS Structures ⚛ Inputs Compatible with TTL levels ⚛ Conventional Logic CMOS Families
⚛ Operation of MOSFET Transistor ⚛ Dynamic CMOS Logic Structures ⚛ CMOS Output Levels

⚛ Low Voltage CMOS Logic Families

⚛ The MOSFET Transistor as a Switch ⚛ Alternative Logic Structures ⚛ CMOS Driving Capability ⚛ Inputs Tolerant to Overvoltages
⚛ Basic Structures of MOSFET Transistor ⚛ Input-Output CMOS Circuits ⚛ Other CMOS Output Structures ⚛ Evolution of CMOS Technology
⚛ MOSFET Propagation Gate ⚛ CMOS input levels ⚛ Power Consumption of CMOS Circuits  
⚛ Pull Up and Pull Down in CMOS ⚛ Non-Driven Inputs and Slow Transition Inputs ⚛ Static Power Consumption  
⚛ The CMOS Inverter   ⚛ Dynamic Power Consumption  
    ⚛ Charging of External Capacities  
    ⚛ Charging of Internal Capacities  
    ⚛ Short-Circuit Current  
    ⚛ Total Power Consumption  
    ⚛ Maximum Power Consumption  

 

 

 

Logic CMOS Families

The Logic families of CMOS integrated circuits characterize the evolution of technology in this field. Initially, each system consisted of a large number of standardized logic circuits (gates, registers, etc.), while in modern systems the whole functionality is concentrated in a few integrated integrated circuits. Thus, the most recent CMOS logic families mainly implement interconnect functions (buffers and transceivers, registers) and individual logic functions (single or double gates).

The following are the basic features of logic CMOS families, from the older to the most recent. Logic families are divided into two categories: the first includes conventional supply voltage circuits (up to 5V), while the second category includes the low voltage CMOS families.

 

 

Conventional Logic CMOS Families

Figure 3-21 below illustrates the main categories of conventional CMOS conventional family feed voltages and their time evolution.

Logic CMOS families

 

Figure 3-21

 

In the early 1970s, the first logic CMOS family, the CD4000 series, was introduced. This logic family offered zero static power consumption over TTL circuits but a very low operating frequency (up to 1MHz). The series 74C followed by integrated circuits equivalent (terminal to terminal) with the corresponding TTLs. These logic families implemented the MOSFET gates with metal gate and were used exclusively in low power applications.

In the 1980s integrated CMOS circuits with transistor gates of polycrystalline silicon (poly) were developed. The 74HC logic family (with performance equivalent to the TTL 74LS series) and the fastest 74AC family (with performance equivalent to the TTL 74AS) were established as the basis for all subsequent designs. These families also have variants (HCT, ACT) with TTL input levels for interfacing with such integrated circuits.

In the 1990s, improved 74AC series versions with better Output Noise (ACQ) performance were introduced, while two similar VHC / AHC families improved the 74HC Series features. Advanced logic CMOS families are available in packages with improved electrical characteristics.

The technology then shifted to the low-voltage logic families, but will be described in a next section.

Here are the key features of the logic CMOS families that were mentioned earlier.

Power supply voltage: Unlike TTL circuits, CMOS logic circuits are fed with a wider range of voltages. Table 3-3 below illustrates these trends for the various logic families:

 

Logic Family

Power Supply Voltage (VCC)

Specifications Provided

CD4000

3 - 15V

5, 10, 15V

74C

3 - 15V

5, 10, 15V

74HC

2 - 6V

2, 4.5, 6V

74AC

2 - 6V

3, 4.5, 6V

AHC/VHC

2 - 5.5V

2, 3, 4.5V

 

 

Table 3-3: CMOS feed voltages

 

The main power characteristics depend on the power supply used, such as logic input and output levels and propagation delay (decreases as the VCC increases). For this reason, the datasheets of the CMOS logic circuits list the operating specifications for a set of different feed voltages.

Older CMOS families can be powered at voltages well above 5V, so they are still being used (especially the CD4000 series) on simple battery-powered circuits. Newer families perform better when powered in the 5V range, while for very low supply voltages (eg 2V), proper logic operation is not always guaranteed.

• Driving ability: The capability of supplying or drain current at the outputs of the CMOS logic circuit for driving a load, with the output voltage remaining within logic states:

 

Logic Family

IOL / IOH (VCC = 5V, CL = 50pF)

CD4000

± 0.4mA

74C

± 1.6mA

74HC

± 6mA

74AC

± 24mA

AHC / VHC

± 8mA

 

 

Table 3-4: CMOS driving capability

 

The sizes in table 3-4 refer to continuous power supply/drain. When switching the output state, the integrated circuit can provide a much larger amount of current momentarily.

From Table 3-4, it is clear that CMOS circuits have symmetrical driving capability at low and high output levels. Older CMOS families lacked the ability to drive. The 74AC Series (or the fastest) can provide the most amount of power.

Factors affecting the propagation delay

 

Figure 3-22

 

Propagation Delay (tPD). A very important feature that determines the speed of the CMOS circuit. The propagation delay depends on temperature, supply voltage and output load (Figure 3-22).

 

logic family

delay tPD (VCC = 5V, CL = 50pF)

74C

70ns

74HC

25ns

74AC

7.5ns

AHC/VHC

8.5ns

 

 

Table 3-5: Maximum propagation delay

 

Logic input levels (VIL, VIH). The logic input levels of the integrated CMOS circuits are VIL = 0.3VCC and VIH = 0.7VCC. These relationships do not apply to very small feed voltages (eg VCC = 2V, VIL = 0.5V and VIH = 1.5V).

Logic output levels (VOL, VOH). They are always defined in relation to specific values ​​of the output current (IOL, IOH).

 

Logic Family

VOH(min), VOL(max) @ IO, VCC

74C

4.35 / 0.4V (± 0.45mA, 4.75V)

74HC

3.84 / 0.33V (± 4mA, 4.5V)

74AC

3.76 / 0.44V (± 24mA, 4.5V)

AHC/VHC

3.8 / 0.44V (± 8mA, 4.5V)

 

 

Table 3-6

Exit noise. As CMOS logic circuits become faster, both the output state alternations and the corresponding sharp current flow cause parasitic voltage spikes at neighboring outputs of the same integrated circuit. In Table 3-7 below, the standard offset values ​​(VOLP) and lower (VOLV) are displayed from the resting level (Figure 3-23) of a constant output of a '244 circuit when the remaining seven outputs simultaneously change the logic level:

 

Logic Family

VOLP / VOLV ( '244, CL = 50pF)

74HC

0.5 / -0.3V

74AC

1.6 / -1.5V

74ACQ

0.9 / -0.5V

AHC/VHC

0.6 / -0.8V

 

 

Table 3-7

 

As shown in Table 3-7, the fastest family noise (74AC) is the largest excursion noise. For this reason, 74ACQ (Quiet Series) uses special circuits in the output stages, with which it gradually changes the shape of the output waveform, thus avoiding the sudden changes in current causing the noise. The output waveform shape control technique is used on all CMOS synchronous circuits.

Hi to Low Output Noise

 

Figure 3-23

 

 

Low voltage CMOS logic families

In the most recent CMOS integrated logic circuits, the supply voltage is less than the conventional 5V voltage introduced by the TTL circuits. Three low voltage power standards have been set for the supply of CMOS synchronous circuits: 3.3V ± 0.3, 2.5V ± 0.2 and 1.8V ± 0.15.

Standard Logic Voltage Levels

 

Figure 3-24

 

The main reasons for introducing lower feed voltages are as follows:

 

  • A) In standard applications of CMOS circuits, the logic output levels are practically equal to the supply voltages (VCC and GND) and the transition from one logic level to the other causes dynamic power consumption proportional to V2CC. Reducing VCC brings significant benefits to power consumption, which is a determining factor in modern CMOS circuits.
  •  
  • B) The dimensions of the MOSFET transistors are constantly decreasing with the state of the art and the level of silicon oxide, which isolates the transistor gate, is getting thinner. Thus, 5V voltages can no longer be applied to the transistor gates without the risk of breaking the isolation level.

 

Conventional CMOS logic families, described in the previous section, can operate at feed voltages of less than 5V with significantly reduced performance in propagation delay and driveability, as shown in the example of Table 3-8:

 

Chip: 74HC244

normal voltage VCC (4.5V)

with minimum VCC (2V)

Maximum propagation delay tPD

28ns

140ns

Maximum driving ability IOL(H)

6mA

0.02mA

 

 

Table 3-8: Effect of supply voltage on operating characteristics

 

To achieve increased performance at low power supply volumes, new logic CMOS families have been developed. These logic families belong to two main groups, depending on the manufacturer. The first group (Fairchild, ON Semiconductor, Toshiba, etc.) offers the LVX, LCX and VCX logic families, while the second (Texas Instruments, Philips and others) the LV, LVC, ALVC and AVC families respectively. Families are reported in ascending order, while the respective members of the two teams are approximately equivalent in performance.

Table 3-9 lists the main charging characteristics of low voltage logic families. It should be noted that each family is designed for optimal operation at a particular VCC voltage. The optimal voltage trend is shifting for the younger families from 3.3V to 2.5V, and there are already commercially available CMOS families (not listed here) with optimal 1.8V output, as well as families that operate at less than 1V supply voltages.

 

Family

LV

LVC

ALVC

AVC

LVX

LCX

VCX

VCC (volts)

2-5.5

1.65-3.6

1.65-3.6

1.4-3.6

2.0-3.6

2.0-3.6

1.4-3.6

complete functional specifications for VCC

2.5

3.3V

2.5

3.3V

1.8, 2.5,

3.3V

1.8, 2.5,

3.3V

3.3V

2.5

3.3V

1.8, 2.5,

3.3V

optimal operation in VCC

3.3V

3.3V

3.3V

2.5V

3.3V

3.3V

2.5V

tolerance overvoltage

5V

5V

5V

3.3V

5V

5V

3.3V

 

 

Table 3-9: Low-voltage CMOS logic families.

 

 

Inputs Tolerant to Overvoltages

The last line of Table 3-9 illustrates a particularly important feature of low voltage CMOS families: the ability of inputs to be driven by voltages greater than VCC. This feature allows direct integration of integrated CMOS circuits with different feed voltages when they coexist in the same system. The use of mixed feed voltages is common in transient design phases, where integrated circuits with different VCC are used.

Direct connection only applies in one direction when the driven circuit is fed with a lower VCC voltage than that of the driving circuit: From Figure 3-24, it appears that for all VCC standards, VOL is smaller than VIL in each case . Also, VOH is larger than VIH when the driven circuit has a lower VCC. In this case, it is sufficient for the input to be overvoltage tolerance, so that it can be connected directly.

Conversely, when the driven circuit is fed with a higher VCC voltage, it is not ensured that VIH will be less than VOL. For low-level signal driving from an integrated circuit with higher VCC voltage, special integrated level shifters must be used. These circuits are powered by two different VCC voltages and translate the logic levels of the signals in both directions.

Inputs Outputs tolerant to overvoltages

 

Figure 3-25

 

Overvoltage tolerance requires some changes to the design of CMOS input devices, as shown in Figure 3-25a.

The surge protector should be omitted because in the case of an input signal higher than VCC this diode will be polarized correctly forming a conductive path between input and VCC as long as the input is at this high level. The absence of the protection passage is offset by the design of the input stage with enhanced current flow resistance characteristics.

Figure 3-25b shows that overvoltage tolerance is also required at the circuit outputs, particularly those connected to channels (three-state outputs). If the bus is driven from another circuit with a VCC above the VCC, then the parasitic capacitance of the PMOS transistor between the drain and the substrate will be polarized, causing a significant amount of current. In the simplified circuit of Figure 3-25b, a special device compares the output voltage with the VCC and leads the substrate to the largest, thus avoiding the correct polarization of the parasitic passage.

3.7.2.2 Characteristics of low voltage supply families. Concluding the presentation of the low voltage CMOS logic families, the driving capability and speed (propagation delay) of these circuits are listed. These features are given for the three standard VCC levels (3.3, 2.5 and 1.8V).

Propagation Delay per VCC

 

Figure 3-26

 

• Dissemination delay: The data refer to an integrated isolation circuit '244. Figure 3-26 graphically depicts the maximum (worst-case) propagation delay for load CL = 30pF. In all cases, the delay increases as the VCC decreases, but the newer AVC, ALVC and VCX families have a smaller deviation in their performance even at 1.8V.

• Driving ability: Figure 3-27 shows the driving capability (maximum steady-state current supply without disturbing the logic states) of the various low-voltage logic families. This power supply is symmetrical (IOL = IOH), as in all CMOS circuits. It is noted that when moving the outputs from one logic state to the other, the dynamically supplied current is larger than the one shown.

Low Voltage Driving Capability CMOS (IOL-IOH)

Figure 3-27

 

 

Evolution of CMOS Technology

The large-scale expansion of CMOS circuits in the field of digital logic is due to the ever-increasing integration: since the introduction of CMOS circuits to date, their speed is increasing while production dimensions and costs are decreasing. Modern CMOS circuits are 20 times faster and occupy only 1% of the silicon surface than the original circuits. The base unit for the dimensions of the MOSFET transistors of commercially available integrated circuits is currently at 0.18μm.

Improvements occur at a steady pace, but they tend to reduce some of the fundamental technological limits:

 

  • • The conventional optical lithography techniques for the construction of integrated circuits are approaching their limits as the dimensions of the transistors are reduced. The required new manufacturing techniques may significantly increase production costs.
  •  
  • • The reduction in the dimensions of the transistors can not continue beyond a certain limit: the level of isolation of the gates can not be reduced below 2nm without losing its dielectric properties, while for the operation of the transistor as a switch it is estimated that the source distance - sink must not be less than 25nm.
  •  
  • • The effect of temperature on ultra-small integrated circuits is important for key operating characteristics such as threshold voltage and leakage current, leading to non-functional transistors.

 

The above reasons lead to the prediction that the current CMOS conventional CMOS completion rate will be halted by about 2015. Thus, a series of technological improvements are being tested for the further development of CMOS circuits:

 

  • • Already have experimentally constructed MOSFET transistors with structures and materials different from conventional ones. New transistor formats exhibit functional characteristics in very small dimensions (up to 25nm).
  •  
  • • The possibility of operating CMOS circuits at very low temperatures (liquid nitrogen cooling) is considered. These temperatures allow a conventional CMOS circuit to double its performance.
  • • New interface layer materials within the integrated circuits regulate the resistance and transmission line capacity, improving the propagation delay.
  •  
  • • Considerable improvement is also possible at architectural level through hierarchical design and better integration of the various parts of a CMOS circuit depending on functionality and operating frequency.