Digital Memories Tutorial (page 2)



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⚛ Permanent Storage Memories ⚛ EPROM - EEPROM and NOR FLASH Memories ⚛ Dynamic RAM (DRAM)
⚛ Read-Only Memories Only ⚛ NAND FLASH Memory ⚛ Multi-Digit Memory Cells
⚛ Reprogrammed Memories ⚛ Random Access Memory (RAM) ⚛ FRAM memories
  ⚛ Static RAM (SRAM)  




FLASH memories, which are the latest technology in reprogramming permanent storage memories, are divided into two categories depending on their structure: NOR FLASH memories and NAND FLASH memories.

The NOR FLASH memories are implemented in a more conventional way and are similar in their basic structure to the EPROM and EEPROM memories. In this section, NOR FLASH memories are considered as a representative formula for EPROM & EEPROM memories, with the differences marked separately.

Each NOR-FLASH memory is organized in the traditional way: the information digits are grouped into words and each digit is stored in an electrically isolated gate transistor. This transistor is uniquely associated with a wordline (WL) and a bit line (BL) as shown in Figure 6-4.

NOR FLASH memory array


Figure 6-4


Figure 6-4 shows that all digits of each word can be accessed simultaneously and their content read from the corresponding digit line (BL). Several transistors of different words are connected in parallel to each digit line.

The functions performed on the transistor digits of a NOR FLASH memory are as follows:


• Reading: each word is randomly accessed in a NOR FLASH memory. Decoding the address of the word leads the selected word line (WL) to a predetermined Vread voltage while the remaining word lines remain inactive. Each pre-charged (BL) line of digits will be discharged via the selected transistor only if it is in '1' mode. The generated current is detected for each digit line and converted to the appropriate binary number by means of detection and amplification circuits. The reading function for each digit line (BL) is proportional to the logic of a NOR gateway (to make BL = '0' one transistor is enough - the selected one - to be '1'). From this fact it gets the name of this type of memory (NOR FLASH).

⇒ The EPROM and EEPROM memories use exactly the same method for reading stored words.


• Programming: writing a '0' to the required transistors of a word. For this function, the word, digit, and sourceline lines of the transistors are driven with the appropriate high voltages. Each word can be programmed in a random order, only if the provided block is previously deleted (see deletion mode).

⇒ EPROMs are not programmable as described earlier. Instead, their UV content must first be completely deleted from the system and then programmed into a dedicated programmer. EEPROMs have circuits for programming a random word just like NOR FLASH memories.


• Delete: (record '1'). Due to the density of the NOR-FLASH memory circuits, it is not possible to delete by word. Instead, deletion occurs in large blocks, which are typically 64KB. As with programming mode, the deletion of selected transistors is achieved by driving the appropriate voltages to the terminals of these transistors.

⇒ EPROMs are completely erased by ultraviolet radiation, while EEPROMs have full erasure circuits of up to one single word individually.

NOR FLASH memories achieve fast access times (65 to 170 nsec), but have slow programming times (7 to 10 μsec/byte) and erase (about 1 sec/sec). External links are associated with standard memory linking (separate address, data and control lines) and are ideal for storing and executing code on the site.

EEPROM memories are implemented with more complex circuits, as long as they allow readings, programming and deletion to each word separately. For this reason, large capacity EEPROM memories are not produced.

Finally, because of the inability to change their contents within the system, EPROMs are only used to develop prototypes or commercial products to store unnecessary data.




The NAND FLASH memories also use the electronically isolated gate transistor to store the bits and achieve the programming and deletion of digits by the Fowler-Nordheim (FN) tunneling method. However, the structure of NAND FLASH memories differs significantly from the structure of memories discussed earlier.

In the NAND FLASH memories each transistor-digit is not uniquely associated with one line of line (BL) and one word line (WL). Instead, the data is accessed by pages and the transistors are serially connected in groups. The organization of a standard NAND FLASH memory is illustrated in Figure 6-5.

NAND FLASH memory array


Figure 6-5


Each NAND FLASH memory is organized into pages. Typical size of each page is 264 (256 + 8) or 528 (512 + 16) bytes. A certain number of pages (typically 16 or 32) compose a block of 4 or 8 KB, while total memory is composed of a number of segments (e.g., 512 segments).

The pages of each section are implemented through a set of serially connected isolated gate transistors, which store the bits, as shown in the right-hand part of figure 6-5. In the vertical column of the transistors, each belongs to a different page and is controlled by a separate page check. The transistor's column is connected at both ends to one line of line (BL) and to the ground via two normal MOS transistors, which here play the role of propagation gate. Any reading or programming function can only be performed simultaneously in one of the serially connected transistors.

In NAND FLASH, the data is not read or written by words. Because of their structure, these functions are made by pages. The data transfer timings and activation of the appropriate signals are internally in each memory.


• Reading: During this operation, an entire page is transferred from the array of transistors to a temporary storage where it will be read in part by the computing system. For transferring the page, the column of the 6-5 transistor is first connected to the two ends with the ground and the corresponding digit line (the propagation transistors are activated). Then all of the page selection lines except the selected are fed with high voltage. The transistor digits are independent of the load of the isolated gate. The line of the selected page is linked to the Vread reading voltage (usually 0V). The corresponding transistor will only run if it is in '1' mode, creating a path from the prefixed line of line (BL) to the ground. By detecting whether or not there is a current flow, reading the particular digit is achieved.

⇒ The operation of the serially connected transistors is proportional to the logic of a NAND gate: the output of the line will be 0 only when all the transistors of the column will run (ie when the transistor of the selected page is in '1' mode and will run). From this resemblance, NAND-FLASH memories get their name.


• Programming: Programming digits is by pages, moving data from the temporary storage. The computer first inputs the write command into the NAND FLASH memory and then transfers its data to the temporary storage. Then the internal circuits of the memory undertake to record the data on the selected page. Prior to writing, the entire block (page) should be deleted (all transistors being '1').

At the transistor level, programming begins by connecting the transistor column to the line (BL). The control pages of the pages besides the selected ones are driven with a positive voltage, while the control line of the selected page is driven by a high voltage programing Vpp (usually 20V). If a transistor has to be set to '0', the corresponding digit line (BL) is lowered and the load on the isolated gate of the transistor comes to '0'. If the transistor has to remain at '1', the corresponding digit line is led to a high level which does not cause a change in the load of the electrically isolated gate.


• Deletion: The deletion of the transistors (reset to '1') is applied in total by segments. All page selection lines are lowered, while the substrate of all the transistors of the segment is connected to a high voltage Vpp. This combination is enough to remove the electron load from the isolated gates, thus setting all the transistors of the segment to the '1' state.

NAND FLASH memories display lower read times than NOR FLASH but are faster in programming and deleting operations. Due to their structure they occupy less silicon surface and can be manufactured with higher density. The data transfer method (by pages) makes NAND FLASH memories ideal for mass storage of data (memory drives, memory sticks, etc.).

A special feature of NAND FLASH memories is that much of them is marketed without having 100% correct operation. This means that there are transistors, which are malfunctioning. For this reason, additional bytes are added to each page, storing information about the proper operation of the page. Application software needs to recognize and avoid parts that are not working properly. Manufacturers guarantee that their NAND-FLASH memories present up to 2% portions with malfunctions.

Completing the presentation of reprogrammed permanent storage memories, the following table summarizes the basic features of the EPROM, EEPROM, NOR and NAND FLASH memories.


Memory Type

Standard Capacity


Change Contents



8-512 KBytes

Word Access: 45-90ns

Total Deletion with UV

Programming with CHE method

Storing Fixed Data

Prototype Development Systems


1-32 KBytes

Word Access: 70ns

Programming: 3-5ms/Word

Erasure and Programming each

Word with FN method

Save that change in Data Words

(E.g., system operating parameters)


1-8 MBytes

Access Keyword: 65-110ns

Programming: 7-13ms/Word

Delete: 1 sec/division

Delete per sections with FN

Programming per word with CHE

Storing a code for direct execution

(execution- in-place - XIP)


1-256 MBytes

Transfer page: 7-25ms

Access Rate (after transfer): 50-80ns/byte

Delete: <50ms/Section

Programming Page: 3-5ms

Erasure and programming

per page with FN method

Bulk data storage


Table 6-1: Features of EPROM, EEPROM, NOR and NAND FLASH



Random Access Memory (RAM)

Random access memory (RAM) is the basic type of memory in the category of non-permanent data retention circuits. These types of memories require a continuous power supply to maintain their data. The structure of this category of memories allows for independent (random) access to each location in the memory, both for read and write data.

Random access memories are divided into two subcategories:


  • 1. Static memories (SRAMs) store the data in flip-flop circuits. As long as a static memory feed is provided, the data is kept on the flip-flop without any additional action being required.
  • 2. Dynamic memories (DRAMs) store the data in capacitance capacitors in the form of charge for each digit. This load must be renewed at regular intervals through a special refresh cycle.


In general, static memories are faster to access but require more space in silicon to construct their circuits, while dynamic memories are slower to access but at the same time simpler to implement the retention circuit of each digit.



Static RAM (SRAM)

The typical embodiment of the basic one-bit storage cell of a six-transistor (6T cell) SRAM is illustrated in Figure 6-6.

SRAM memory cell with 6 transistors (6T cell)


Figure 6-6


Pairs of transistors T1p/T1n and T2p/T2n are essentially two CMOS inverters. The input of each of the two inverters is connected to the output of the other, thus forming a very simple D flip-flop circuit. This flip-flop stores the bit.

The outputs of the two inverters are also connected to the digit line (BL) and the complementary line (BL '). This connection regulates transistors T3 and T4, which are controlled by the word line (WL) corresponding to the particular memory cell. The two lines (normal and inverted) are connected in parallel with a number of memory cells and show a certain parasitic capacity in their length.

The process of reading the stored bit from the memory cell is as follows:

• Assuming that the stored digit is initially '1' then at point A (see figure 6-6) the voltage is high (HIGH). T1p is cut off while T1n is running, resulting in point B being at low voltage (LOW). So T2n is cut off while T2p is running and the high potential generated is fed back to point A, keeping the bit. The word line (WL) is inactive and T3 and T4 are cut off, disconnecting the cell from the bitline lines.

• As a first step for the read procedure, the BL and BL lines are pre-loaded at high potential. The preload is interrupted before the next action, but the load is maintained due to the parasitic capacity of the BL and BL 'lines.

Then the word line (WL) is driven to a high potential and the transistors T3 and T4 run, connecting the memory cell to the digits. Since point B is LOW and T1n conducts, the complementary line (BL ') is discharged through T4 and T1n and low-potential. Normal Line Number (BL) remains at high voltage.

• The difference between BL and BL 'is detected and amplified by a special sense-amplifier, which produces the output bit. It should be noted that if the stored digit was '0' then the reading would be exactly the same, with only the opposite values ​​on the BL and BL' lines.

The process of writing a new bit to the memory cell is as follows:

• Assume that the initial state of the memory cell is as described previously (the stored digit is '1'), and that the new digit to be recorded is '0'.

• The BL line is driven at low potential and the BL 'line at high. Line driving is "strong" and does not interrupt as preloading during reading.

• Then the word line (WL) is driven at high potential and T3 and T4 are driven. Point A is forced to descend to a low potential, leading T1p to run and T1n to cutoff. Thus point B acquires a high potential (although it has already been led to HIGH, through T4 by BL '). Also, T2n runs, while T2p is cut off, thus enhancing the low potential of point A.

• By completing the registration process, the word line (WL) returns to a low potential by cutting the memory cell from the digits. The new bit has already been stored on the two inverters of the cell. The same procedure is used to enter the '1' digit with reverse BL and BL 'driving values.

In addition to the SRAM with six transistors previously described, SRAM cells of different design are also used. The cell with four transistors and two resistors (4T + 2R cells) replaces the large pMOS transistor (T1p and T2p in Figure 6-6) with high-value resistors (GΩ), achieving a lower surface per SRAM cell. In even more modern memories, the two resistors are replaced by thin-film-transistor (TFTs), which are placed above the other four cells.

The manufacturing process of the above-mentioned alternative cell types is non-standard, making it difficult to integrate this type of memory into larger circuits. Moreover, as modern design reduces the cell dimensions on a silicon surface, the lesser the space advantage these alternative designs offer over the base 6T cell. In smaller dimensions, the 4T + 2R cell presents stability problems. For all the above reasons, the use of 6T cell has been generalized in modern designs.

SRAM memory array


Figure 6-7


Figure 6-7 illustrates the basic structure of SRAM memory cells. Each cell is connected to the line (BL and BL ') and a word line (WL), which is driven by the address decoder accessed. In each pair of digits, many cells are linked, from different words each, to a cell column.

At one end of the column there are the appropriate circuits for preloading and driving the BL and BL 'lines during the read / write process. Pre-charging uses pMOS transistors, which are suitable for carrying a charge from the supply voltage (VDD).

At the other end of each cell column a special sensing and amplification circuit is connected. This circuit is necessary because when reading the contents of the cells, the BL and BL 'lines acquire HIGH and LOW voltage levels but never reach full voltage levels (VDD or ground). The sensing-amplification circuit enhances the potential difference between the BL and BL 'lines to reproduce the output bit with integral VDD or GND voltage levels. One type of such a circuit is described in Figure 6-8.

Differential Sense Amplifier


Figure 6-8


Assuming that the BL line voltage is high (HIGH) and the BL line low (LOW) and that the sensing input is LOW, then the T1n and T2p transistors are driven while the transistors T1p, T2n and Ts are cut off. The BL line is driven by HIGH to 'intact' VDD voltage through T2p. By setting the sense HIGH, the BL ' line through T1n and Ts is driven by LOW on the ground. In essence, the differential amplifier normalizes HIGH/LOW voltages in VDD/GND, based on the potential difference between BL and BL '.

SRAM memories are the fastest read-write memories and are used in applications where fast access to the contents of memory is required. They are produced in sizes from 32Kbytes to 2Mbytes and have a word range of 8 to 72 bits. Power consumption is a function of the SRAM speed and ranges from 100μA to 5mA in standby mode, while when the memory is active, the consumption ranges from 40mA to 150mA.

As for the connection of SRAMs with the rest of the computing system, we distinguish two categories:


  • • Asynchronous SRAMs (read or write) are controlled by external signals. Once a control line is triggered, the memory starts the corresponding function and produces data (if read) in a time period similar to its internal construction. The fastest SRAMs of this type have an access time of 10 to 20ns at most.
  • • Modern SRAMs produce results by following the cycle of a clock signal. The structure of these memories allows the duplication of sequential read/write operations (pipelining). Each access is divided into two or three stages, serving a corresponding number of accesses at the same time. In this way, modern SRAMs can produce new data in each clock cycle, achieving 200MHz and minimum access times of up to 2.5ns. Modern SRAMs are used to set up cache memories.



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