Digital Memories Tutorial (page 3)

  

 

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⚛ Permanent Storage Memories ⚛ EPROM - EEPROM and NOR FLASH Memories ⚛ Dynamic RAM (DRAM)
⚛ Read-Only Memories Only ⚛ NAND FLASH Memory ⚛ Multi-Digit Memory Cells
⚛ Reprogrammed Memories ⚛ Random Access Memory (RAM) ⚛ FRAM memories
  ⚛ Static RAM (SRAM)  

 

 

Dynamic RAM (DRAM)

Dynamic read/write (DRAM) memory modules use memory cells with four, three or one transistor. From these three types, the design with the one transistor per one cell has prevailed, especially for large-capacity DRAMs.

transistor Cell and DRAM memory arrangement

 

Figure 6-9

 

The DRAM cell with a transistor is illustrated in Figure 6-9a. Because of its simplicity, the cell occupies little space and is suitable for building large capacity memories. Within the cell, the CS capacitor stores the charge representing a bit. Unlike the parasitic CBL capacity that the (BL) digit line has, the CS capacitor must actually be built. This is achieved by adding a layer of SiO2 dielectric, either directly on the stacked storage cell or in the trench storage cell.

The load on the CS capacitor is not kept constant. Instead, the capacitor is discharged after a certain amount of time. To maintain information in a DRAM requires periodic refresh of the charge of all the cells contained in the memory.

Figure 6-9b schematically illustrates the typical structure of a DRAM. A number of memory cells (typically 256 or 512) are connected to a vertical BL line. Line load BL is detected and amplified by a special amplifier circuit (SA). The sensing amplifier works differentially, so it needs to compare two-line loads. Unlike the SRAM static memory cell, which was described in Figure 6-6, the DRAM cell is connected to a single BL line. For this reason, a pair of BL lines are connected to each sensing amplifier (SA). Each pair of BL lines, together with the SA amp and the corresponding pre-charging circuits, form a storage column. The memory cells are alternately connected to one of the two BL lines of the column.

A part of the address entered into the memory is used in the line decoder for driving horizontal word lines (WL). Each line WL selects a cell from each column (the columns are usually 512 or more). The rest of the address is used to select the column, the content of which will eventually pass to the memory output lines. Many row-column tables, such as those in Figure 6-9b, can be included in parallel within a DRAM.

In conventional DRAMs, the access address is multiplexed: first the line address and then the column address through the same pins. Synchronization is achieved through the RAS (row address strobe) and CAS (column address strobe) control signals. These signals are contractually active at low (low). The time multiplexing of the address does not introduce substantial delays in accessing the contents of the memory because of its internal mode. Instead, the number of required terminals is reduced to enter the address. DRAM function control over each system assumes external integrated circuits (DRAMs).

The data reading function from a DRAM is as follows:

• All BL lines are preloaded at VDD/2 voltage (this value is related to the method of detecting the digit, as will be shown below). Lines belonging to the same pair are electrically connected to ensure they have exactly the same load. Pre-charging the BL lines takes care of pre-charging circuits (Figure 6-10b). Preload occurs before each memory access when the RAS signal is inactive (RAS precharge time - tRP, see timing chart in Figure 6-10a). Before the next step the preload stops.

• The line address, signaled by the RAS signal, which goes to a low level, is then entered into the memory. The address is stored in the memory and feeds the line decoder (Figure 6-10c). The selected word line (WL) is driven to a high potential. The transistors of all cell lines run, connecting each CS capacitor to the corresponding BL line.

• If the CS capacitor is discharged (the digit is '0') then a small part of the BL line load charges the CS while the line BL potential decreases accordingly. If CS has a load (digit '1') then some of it moves to line BL and CS is almost discharged (because the parasitic capacity of the BL line is much larger than the CS capacity). The potential of the BL line increases by a small percentage. The second line of the BL pair remains at VDD/2 potential.

• At the edge of the BL line the sensing amplifier (SA) detects the potential difference of the BL line from the second pair that has remained in VDD/2 and amplifies it. In DRAMs, this difference is at most 100-200mV. If BL is slightly larger than VDD/2, it is driven to VDD voltage. If slightly smaller, it leads to ground.

• The amplified potential value generated by the sensing amplifier is fed back to the BL line and as long as the WL line is still active, the CS initial load is reshaped (which is altered when the CS is connected to the BL line).

• The column address is then entered into the memory. This is signaled by the transition of the signal CAS to a low level. The minimum time between signaling RAS and CAS is called tRCD (RAS-CAS-Delay). The column address is internally driven into memory in the column selector, which selects those sensors (SA) outputs which will pass to the memory data output (Figure 6-10d).

• Finally, the line decoder, column selector, and SA amplifiers are deactivated. The load of the capacitors is isolated within each cell and the memory is ready to start pre-charging again. In total (see Figure 6-10a), the time from activation of the RAS signal to the display of the output data is denoted by tRAC (row access time) and equals the time of accessing the DRAM. The minimum time between two successive accesses (access cycle) is tRC.

DRAM Memory Read Mode

 

Figure 6-10

 

The recording of new data at one DRAM location is somewhat similar:

 

  • • BL lines are preloaded after previous access.
  •  
  • • The line address and data to be recorded are entered into the memory. Along with the RAS signal, the WE (write enable) signal is also activated.
  •  
  • • The cells of the selected line are linked to the BL lines, as in the case of reading. At the same time the data to be recorded is forwarded to the column selector.
  •  
  • • Then enter the column address along with the CAS mark. The column selector drives the digits to be recorded in the corresponding SA amplifiers. The value of the digits passes through the selected SA amplifiers on the corresponding BL lines, thus changing the load of the selected cells to the new values.
  •  
  • • For the BL lines of unselected columns, the function is identical to that of reading: the corresponding SA amplifier simply enhances the content of the selected cells.

 

As mentioned earlier, the main feature of DRAM is that the load on the CS capacitor is not sustained indefinitely. Because of the leakage current that occurs through the cell transistor, the capacitor is discharged after a certain amount of time. To maintain information in a DRAM requires periodic refresh of the charge of all the cells contained in the memory.

Load refresh function is equivalent to a periodic reading (without returning data) of the cell content of each line. The refresh period of each word depends on the internal structure of the memory and ranges between 16 and 128msec. The lines are updated successively at regular intervals. The number of lines to be renewed before the refresh process is repeated for the same line and is called "refresh cycle" and is denoted Ref. (For example DRAM with Ref.4K means that the refresh process is repeated for 4096 lines). Various DRAMs support three main refresh methods (Figure 6-11):

Methods of renewing DRAM

 

Figure 6-11

 

• RAS-only refresh: This refresh is exactly the same as the read process. When the signal RAS is activated, the address of the refresh line is entered. As in the case of reading, the cells of the selected line are associated with their respective BL lines and sensing amplifiers (SAs). The cell load is amplified and returned to the CS capacitors. Instead of reading, however, the CAS line is not triggered, so no data is displayed in the memory output. After renewal, the BL lines are preloaded for the next access.

• CAS-before-RAS refresh: This type of refresh is different. In this case, the CAS is activated for a short while the RAS signal is inactive without entering a refresh address. The memory control logic recognizes this combination as a "refresh command" and generates the next refresh address via an internal counter. The renewal is then performed as in the previous case.

• Hidden refresh: Immediately after a normal access, the CAS signal remains active. The new RAS/RAS activation causes a new regeneration address to be created internally in the memory and the start of a refresh cycle. This method always associates a refresh cycle with a previous access cycle, and assumes that the memory processor bus frequency is low enough to complete the refresh before the next access. For this reason, this is not used in today's fast memory channels.

Only DRAMs are used to implement the main memory of each computer system. The operating speed of DRAMs greatly determines the performance of the overall system. As microprocessors increase their operating rate, it is also desirable to increase the performance of DRAMs.

Conventional DRAMs, described earlier, achieve access times of 70 to 80ns. This time is required by activating the RAS signal until the data are shown at the memory output.

While maintaining the basic structure of a DRAM, several variants are designed to reduce data access time. These variants utilize burst mode, where data from successive addresses is transferred sequentially between the processor and the main memory. These different DRAM architectures are the following (in order of appearance):

• FPM DRAM (Fast Page Mode DRAM): These memories improve the performance of conventional DRAMs by utilizing the availability of ready data on SA amplifiers after each access. Figure 6-10c shows that when accessing a line in memory, SA enhancers descend the contents of all the cells connected to this line. The column selector then selects some digits to appear in the output. FPM DRAMs allow the successive selection of different columns (repetitive triggering of the signal CAS) on the same line without reloading the BL lines and entering a line address. Eliminating these processes reduces access time for access to the same line (or page) at 40ns.

• EDO DRAM (extended data out DRAM): A further improvement is achieved by adding cache data to the memory output. Typically the reading data remains at the memory output as long as the CAS signal is active (see Figure 6-10a). The addition of the registers allows for a quick turn off of the CAS and start a new access cycle faster than before. This improvement occurs only during reading and allows access times up to 25ns. Memory of this type is available in capacities ranging from 16 to 64Mbit.

• SDRAM (Synchronous DRAM): Designing DRAMs that synchronize their operation with an external clock signal allows for reduced access time to bursts at 15ns per access cycle. SDRAMs have a completely different architecture than previous asynchronous types, which are controlled by the RAS and CAS signals. The SDRAM memories combine the CS (chip select), WE (write enable), RAS and CAS (input) commands into the memory. These commands enable the corresponding function (preload, line selection, reading, refresh record) always synchronized with the clock signal. SDRAMs combine additional architectural features:

 

  • a) duplicate memory banks that allow overlapping operation (one portion preloaded at the same time as the second one is accessed for reading or writing); and
  •  
  • b) internal control registers, which are programmed with the desired function characteristics (read/write burst size, single word or burst record, required cycles to display the data from the time of [CAS latency, 2 or 3 cycles] and other Characteristics). SDRAMs are available with capacities ranging from 64 to 512Mbit.

 

• DRDRAM (direct Rambus DRAM): the memories of this type use a completely different packet request/response protocol to communicate with the rest of the system. Addresses/commands and data are transferred via different lines to both edges of a clock signal (ascending and descending edge). Internally, each memory is divided into many layouts (up to 32), allowing for parallel access. DRDRAMs are available in a standard 128 / 144Mbit capacity and can achieve a 1.25ns/2 bytes (or 1.6GB/s) access time.

 

 

Multi-Digit Memory Cells

In attempting to increase the capacity of different types of memory, two-digit storage technology is currently used in some NOR FLASH memory products in each memory cell. Conventional FLASH memories store their data in an isolated gate transistor (see figure 6-3). Each bit is represented by the presence of a charge on the isolated gate, which load affects the VT transducer voltage of the transistor. For storing two digits on each transistor, it is enough to load the isolated gate into four different levels, which represent the digits '00', '01', '10' and '11'.

Charging the isolated gate at four (instead of two) levels requires a precise method of programming the transistor. In practice, during programming, a series of voltage pulses are applied to the saturation transistor while controlling the VT. At each programming pulse, approximately 3,000 electrons are transferred to the isolated gate. Programming is completed when the VT conduction voltage reaches the desired level.

For both programming and reading, exact load detection of the isolated gate of each transistor is also required. The detection is accomplished by comparing the load of the transistor with some reference transistors. These transistors have been programmed with great precision during memory construction, so as to provide reference levels for comparison (Figure 6-12).

Multi-digit memory cell load detection

 

Figure 6-12

 

A voltage VREAD is applied to the gate of the read transistor and the reference transistors. Depending on the load of each transistor, a current passes through it. The higher the VT conduction voltage of each transistor, the smaller the current being displayed. Three sensors amplifiers compare the current of the read transistor to that of the reference transistor and drive the logic circuit that produces the final digits D0 and D1.

In addition to the already available multi-digit FLASH, research is moving towards the development of corresponding DRAMs with more than one digit storage per memory cell.

 

 

FRAM memories

In the field of non-volatile memories, commercial products have been developed that use ferroelectric RAM - FRAM or FeRAM technology. This technology stores one bit in a thin crystalline structure. This structure can be maintained in two situations, depending on the location of an agile atom in the center of the crystalline structure. For moving this atom to one of two possible states, it is sufficient to apply an electric field to the surface of the crystal.

The crystalline structure is used in FRAM memories, just like the capacitor in a DRAM (see Figure 6-9a). In FRAM, however, the state of the crystal can be maintained even when the memory supply is interrupted.

For reading a bit in a FRAM memory, an electric field is applied to the ends of the crystalline structure. The agile atom in the center of the structure will move in the direction of the field, unless it is already in the right position. Position change produces a slightly higher load than if the atom does not change position. This difference is detected and converted to the appropriate bit. As can be seen, reading can alter the state of the crystal. For this reason, immediately after reading, the crystals are restored to their original state. Recording is simpler, as new data is simply transferred to the crystals, changing their status if required.

The existing 256Kbit FRAM memory products use two transistors and two crystal (2T-2C cells) to reliably store a bit (figure 6-13a). In both crystals the digit is stored in its normal and complementary form, allowing differential scanning of loads in each reading.

FRAM Memory Cells

 

Figure 6-13

 

The next FRAM products will use a transistor and a crystal (1T-1C cell) (Figure 6-13b) to design memory of greater density and capacity. Crystal design requires advanced detection methods when reading, using predefined reports to compare the load.

The biggest advantage of FRAM is the fast data recording time compared to other fixed storage memories. Each FRAM has an equal read and write time of about 100ns, while for the other fixed storage memories the write time is in the order of msec.

Moreover, the write or read process does not burden the crystal, as opposed to the isolated gate transistors of other permanent storage memories. For this reason, every crystal can be accessed 100,000,000 times for writing or reading (compared to 100,000 to 1,000,000 times of other permanent storage memories - but this limit applies only to programming rather than reading) . Also, FRAM memories require far less energy to write data than other permanent storage memories.

FRAMs in their current form are suitable for low power applications with short recording times: for data acquisition systems, high noise environments and non-contact identification cards (radio frequency activation).