Digital Signal Integrity Tutorial (page 2)
|Page 1||At this page (2)||Page 3||Page 4||Page 5|
|⚛ Noise Output Levels||⚛ Problems Caused by Ground Bounce||⚛ Termination of transmission lines||⚛ Driving Interconnecting Channels||⚛ Interaction of Signals (Crosstalk)|
|⚛ Peak Totem-Pole Current (Crossover Current)||⚛ Ground Bounce Noise Troubleshooting||⚛ Termination Method on the Load Side||⚛ Distributed Channel Line Capacity||⚛ Differential Signal Transmission|
|⚛ Charging Current/Discharge Capacity Output||⚛ Signal Loopback||⚛ Termination at Source Signal Side||⚛ Termination of Channel Lines||⚛ Evolution of Differential Transmission Technologies|
|⚛ Ground Bounce||⚛ Transmission Lines||⚛ Summary of Use of the Different Termination Methods||⚛ Logical Interconnection and Bus Drivers Families|
Problems Caused by Ground Bounce
The ground bounce greatly reduces the quality of the digital signal, and is one of the main causes of operating errors. The problems that can cause the ground bounce is:
a) Incorrect input values (Fig 5-5A): The threshold level (VT) of the integrated circuit B (for discriminating the logic level), is having as reference the (internal) ground voltage. When it shifts due to rebound, just the same happens with the value of the threshold voltage. The shift of the threshold voltage is likely to cause erroneous "interpretation" of fixed input values from other integrated circuits.
b) Displacement of the output channels (figure 5-5b): The outputs of each digital integrated circuit are connected directly (especially in CMOS output stages) with the internal ground voltage (for outputs of low logic state) or power feeding (for outputs a high state). Any bounce internal ground voltage will appear on all outputs LOW, and the corresponding supply voltage bounce affects all outputs HIGH, possibly causing the output levels outside the guaranteed ranges.
Ground Bounce Noise Troubleshooting
The examples in the previous paragraph are the worst case of problems that may cause the ground to bounce. However, even when the voltage changes are not such as to cause immediate errors, the generated digital signal is always of low quality and high noise, especially in high-speed digital circuits. That is why addressing the phenomenon is imperative.
The bounce of the ground can not be completely eliminated, but can be minimized. It is dealt with:
- a) when designing the integrated circuit
- b) when using this circuit.
Manufacturers of the integrated circuit receive some precautions so that their product exhibits as low a degree of ground bounce as possible. Integrated circuits currently use sophisticated types of packages with reduced parasitic inductance per pin. Also, high speed integrated circuits have more than one terminal for the ground and power lines. These terminals are distributed uniformly and as close as possible to the silicon inner surface. This reduces the parasitic inductances as well as the current flowing through each terminal.
In addition to controlling the parasitic inductors, measures are taken to limit the current flowing through the output stages. As mentioned in the previous paragraph, this current is proportional to the potential difference between the LOW and HIGH logic stat, as well as the rate of change of the output status. Thus, the CMOS output stages with full output level changes from VCC to GND produce more noise. Instead of these levels, TTL stages or even lower levels are used to minimize current when changing outputs.
Also, modern output stages are specially designed (often with the addition of internal current limiting resistors), so that the output edge rate can be controlled. This adjusts how quickly the output capacities are charged/discharged and hence the rate of change of the current flowing through the output stage. By controlling the change of current, the potential developed in the parasitic conduits at controlled levels is maintained.
The above mentioned measures are taken when designing an integrated circuit. Respective care is also required when using it on a printed circuit board. If the lines of ground and/or power in the printed circuit are not properly designed, the bounce of the potential is multiplied and can also affect neighboring integrated circuits.
The lines (conductors) of a printed circuit, always show parasitic inductances. These parasitic inductances become critical as the operating speed of digital circuits increases. A direct consequence of parasitic inductance is the occurrence of ground bounce not only inside the integrated circuits but also on the printed circuit lines.
The main method of dealing with ground leakage is to use ground conductors with as little insufflation as possible. This is achieved by using whole ground levels (multi-layered printed circuit boards) with as uniform geometrical characteristics as possible and with less discontinuities and incisions.
At very high speeds, however, even minimal inductance of grounding levels is unacceptable. For this reason decoupling or bypass capacitors are used from 10nF to 100nF between the ground and power terminals. These capacitors act for a short time as local load storage for the ground and power terminals. Thus, the output stage currents do not circulate up to the system power supply, but only from/to the adjacent decoupling or bypass capacitor. The length of lines of ground/power and the parasitic inductances should be minimized, then the bounce potential developed therein is also significantly reduced.
Particular care must be taken to ensure that the decoupling capacitors are as close as possible to the ground-power terminals of each integrated circuit. Otherwise, the capacitor connectors with the integrated circuit add their own parasitic inductance to the circuit.
Finally, for each application, the appropriate logical family should be selected according to the required driving ability. Output stages with a driving capability greater than necessary do not add to the system, but add only noise, as they flow through stronger currents and the ground jump is longer.
The description of phenomena that occur when changing the output level of a digital circuit is completed by reference to a related topic: the return of the current when transmitting a signal.
The current flowing from the output stage to the driven circuit to change the logic level of a signal must eventually return back to the drive circuit by forming a closed loop current. The return of the current is usually done through the ground lines.
In modern high-speed digital systems, return loops, which are large in size, are significant sources of noise and electromagnetic interference. For this reason, the surface enclosed in return loops must be as small as possible, or else the return line should be as close as possible to the transmission line of the signal.
The use of entire ground and power levels below the signal conductors in multi-layer printed circuit boards (PCBs) is the main technique for reducing loopback loops. Because of the electromagnetic fields, the return signal tends to move just below the signal conductor, minimizing the area of the surface enclosed in the loop.
To transmit the digital signal from the output of a circuit (source) to the input of the next (load), some type of conduit is used. From a physical point of view, along the conduit (at the boundary between conductive and non-conductive material), varying electric and magnetic fields are growing, which carry a wave of electromagnetic energy from the source to the load.
Each transmission line is characterized by specific inductance values, capacity, conductivity and resistance per unit length. At the operating frequencies of digital circuits (1MHz or more) the conductivity and the line resistance are negligible compared with the inductance and capacitance. Thus, the transmission line can be represented by the model of Figure 5-6:
The transmission line is fully characterized by the values (per unit length) of inductance (LO, in nH/cm) and capacity (CO, in pF/cm). When moving the electromagnetic wave, LO inductance and CO capacity determine the current flow and potential growth in the line at all times.
It should be stressed that each transmission line is actually composed of a pair of lines. In Figure 5-6 the pair consists of:
- a) The interconnection line of the two circuits
- b) The common reference line (ground).
Based on the model of Figure 5-6, it is assumed that there are no losses in line (lossless line). This practically means that the digital signal is transferred from the input to the output of the transmission line with the minimum distortion, after a certain time delay. Also, the transmission line has no direction: any end of the line may be "input" or "output".
The propagation velocity (velocity of propagation - VP) signal from one end of the line to another is dependent on the dielectric (insulating) material surrounding the conductor, since energy moves actually around the conduit. The maximum propagation speed (equal to the speed of light) is achieved when the conduit is surrounded by air or vacuum. The propagation velocity is given by:
VP = 1 / √(Lo * Co)
And is usually expressed as a percentage of the light velocity (c = 3 * 108 m/sec or 30 cm/ns). Often, instead of the propagation velocity, the inverse size is given, which is the time that is required for the crossing of a unit length of the line. This time is designated as tP (propagation delay) and is measured in ns/cm or ps/cm.
In addition to the propagation velocity, each transmission line is characterized by another size, called "characteristic impedance", and denoted as Zo. The characteristic resistance is given by the relation:
Zo = √(Lo / Co)
The characteristic resistance Zo depends on the geometry and the transmission line materials. As long as these materials remain the same, Zo is independent of the length of the line. Zo is measured in Ohms.
The characteristic Zo resistance is of fundamental importance for the transmission line model, as it was previously shown, because the voltage-to-current ratio (V/I) at any point on the line and at any time is equal to Zo.
Figure 5-7 illustrates various types of conductors along with representative Zo and vP values. Coaxial cables consist of an internal conductor surrounded by dielectric material, an external conductor (shielding) and its insulating casing. Pipeline pairs are available in various shapes and consist of multiple conduits with insulating casing. Finally, there are two standard types of conductors on printed circuit boards (PCBs):
- a) on the surface of the board, with reference to an underlying ground plane (microstrip), and
- b) between two striplines. The propagation velocity is greater in the case of the microstrip, because a part of the conductor does not contact the dielectric material of the board.
When transmitting high frequency signals over a transmission line, there are some phenomena that can not be analyzed through classical circuit theory. The study of these phenomena is necessary to maintain the integrity of digital signals and reduce noise. In the following paragraphs, the main phenomena of the transmission lines are analyzed and ways of dealing with the problems are presented.
As the digital signal crosses a transmission line, reflections are generated when it encounters Zo characteristic change or discontinuity points. The arrangement of Figure 5-8 is used to explain the reflection phenomenon.
In figure 5-8, the output of a digital circuit changes from low to high (from 0 to Vo volts). The output stage of this circuit has an internal impedance (output impedance) Ro and is connected to the end A of a transmission line with a characteristic resistance Zo.
As soon as the output voltage changes, at point A an initial voltage VA0 is displayed which is equal to:
VA0 = ( Zo * Vo ) / ( Ro + Zo )
Due to the voltage divider formed by the resistors Ro and Zo. The voltage front VA0 is called the "incident wave" and propagates through the transmission line to point B.
The V/I = Zo relation at each point on the line for each time point is applied to the forward face transmission. When the signal reaches the end B after tAB, it encounters the RI internal input impedance of the driven circuit. At that point the V/I = Zo and V/I = RI relations must be satisfied at the same time. If RI equals exactly Zo, then the transferred energy is completely absorbed. Otherwise, a portion of the front is reflected back to point A.
The width and polarity of the reflection is described by the reflectance coefficient (ρ) which is given by the formula:
VA0 = ( Zo * Vo ) / ( Ro + Zo )
for every point of change of the characteristic resistance of the line from Zo to R.
If point B was short-circuited (connected directly to ground, R = 0), the factor ρ would be equal to -1. A voltage equal but opposite polarity, to the one that reached point B, would set the voltage at point B and then propagate to point A.
If point B was an open circuit (no connected load, R = ∞), ρ would be equal to 1. A voltage equal and the same polarity of the one that arrived at point B would double the voltage to B and then propagate towards point A.
In the embodiment of Figure 5-8, point B is connected to the RI input impedance of the driven circuit. RI with typical values of 10-20MΩ is much higher than Zo (50-100Ω) and so is ρ ≈ 1. The voltage at point B, which is now equal to VA0, is doubled, while a voltage front VA0 is transmitted Towards point A.
When the reflection front reaches point A, the characteristic resistance changes from Zo to Ro. If the Ro value is different from the Zo, a part of the reflection face will return to point B, possibly with different polarity.
The phenomenon will continue to repeat and the voltage at point B will oscillate until it reaches its final equilibrium value. The changes in voltage at point B will occur every 2 * tAB (time required to cross the signal the distance from B to A and back to B, round-trip delay). The longer the transmission line, the later the voltage at point B will reach its final value.
Signal wave ripple is an important source of noise in the overall system. In addition, if the guided line is a clock signal, false triggering of the driven logic circuits may occur.