# Digital Signal Integrity Tutorial (page 3)

 Page 1 Page 2 At this page (3) Page 4 Page 5 ⚛ Noise Output Levels ⚛ Problems Caused by Ground Bounce ⚛ Termination of transmission lines ⚛ Driving Interconnecting Channels ⚛ Interaction of Signals (Crosstalk) ⚛ Peak Totem-Pole Current (Crossover Current) ⚛ Ground Bounce Noise Troubleshooting ⚛ Termination Method on the Load Side ⚛ Distributed Channel Line Capacity ⚛ Differential Signal Transmission ⚛ Charging Current/Discharge Capacity Output ⚛ Signal Loopback ⚛ Termination at Source Signal Side ⚛ Termination of Channel Lines ⚛ Evolution of Differential Transmission Technologies ⚛ Ground Bounce ⚛ Transmission Lines ⚛ Summary of Use of the Different Termination Methods ⚛ Logical Interconnection and Bus Drivers Families

## Termination of Transmission Lines

Modern digital circuits have the ability to drive a 5V signal at loads above 50pF, maintaining the logic level change time close to 1ns. At these operating rates, the phenomena of the transmission lines are inevitable.

In order to avoid reflections on a transmission line, the line must terminate at its output (point B in figure 5-8) with a RT resistor exactly equal to the line resistance ZO. In this case, the reflectance factor ρ is equal to 0 and the energy transported is fully absorbed by the RT resistor without further reflections being generated.

The matching of ZO with the additional impedance (mainly resistors), is basic for all techniques of eliminating or reducing reflections on transmission lines. By adding these components, the line is terminated (line termination). The various termination techniques will be presented in the following paragraphs.

However, since all termination techniques require additional data and generally increase power consumption in the system, they only are applied when necessary. The need to terminate a transmission line depends on its length and the frequency of the transmitted digital signal.

A transmission line does not require termination when its length is "electrically" small, i.e., the rise times (tr) and descent (tf) of the digital signal are greater than the time the signal needs to cross the line. If this is true, it is assumed that the conductor does not behave as a transmission line, but as a single node, where current and voltage are calculated by classical circuit analysis. In this case, phenomena such as reflections do not affect the integrity of the signal.

The empirical rule applied to determine if a pipeline behaves as a transmission line is given by the formula:

tr < α * tPD

Where tr is the minimum of the rise and fall times of the signal and tPD is the time it takes for the signal to cross the conductor. The coefficient α usually has the value of 2 (2 * tPD is the time it takes the signal to cross the line and return the first reflection back), while in critical designs it can take the value 4, taking into account the second reflection of the signal.

If the above relationship is true then the conductor will behave as a transmission line. Otherwise, the reflections are negligible and no "termination of line" is required.

By replacing the factor tPD with the product of (tP * L), where tP is the required propagation time in the unit length of the line and L the length of the conductor, we end up in the relationship giving the maximum length of conductor that will not behave as the transmission line and does not require termination:

Lmax = tr / ( α * tP )

TP depends on the type of conductor, while tr is the family of the digital driving circuit. In the following table 5-2, the maximum permissible length of a microstrip conductor on a printed circuit board with dielectric material FR-4 (Epoxy / Glass) and dielectric constant 4.6, where tP = 56ps/cm is given as an example.

 Conductor: FR-4 microstrip     tP = 56ps/cm technology TTL CMOS ECL logic family LS ALS FAST HC FACT 10H 100K tr(ns) 6 3 2 4 2 1 0.7 Lmax (a = 2) (cm) 54 27 18 36 18 9 6 Lmax (a = 4) (cm) 27 13 9 18 9 4 3

Table 5-2

When the length of the conductor exceeds the maximum allowed for the logical family used, it is necessary to terminate the line. There are termination techniques with the addition of components both on the load side (driven circuits) and on the signal source side (driving circuit). These techniques are presented below.

## Termination Method on the Load Side

The simplest termination method is called "parallel termination" and is implemented by adding a RT termination resistor to the load side, between the transmission line and the ground (Figure 5-9a). The RT resistor equals the ZO characteristic impedance of the transmission line, so the reflection coefficient at the input of the load is 0.

Parallel ending of transmission lines simplifies the design of the system but also has serious drawbacks:

• A) Power consumption is increasing. Because the characteristic ZO of the transmission line is small (50-100Ω), the value of the RT should also be in respective levels. The low value of RT entails increased current and power consumption in one logical state of the output. For example, for a high 5V level, power consumption over a 50Ω RT is ½W. This consumption is multiplied by the number of terminated lines and is not acceptable in low power systems and battery-powered systems. Also, the output ranges of many logic families (such as common CMOS circuits) can not provide the increased current required by this termination method.
•
• B) Termination in the ground disturbs the correct DC polarization of the line by reducing the signal level VOH and the noise tolerance of the driven circuit respectively. Termination in the ground also alters the duty cycle of the signal. In general, the use of parallel termination requires special attention so that the VOL(max) and VOH(min) of the driving circuit are not violated.

Figure 5-9

The failure to adjust the correct polarization of the transmission line, is easier to deal it by using "Thevenin Termination" (Figure 5-9b). Two terminating resistors, RA and RB are used in this method. The RA connects the line to the supply voltage V+, while the RB is grounded.

Due to the alternating level of the digital signal on the transmission line, the combination of the two resistors equals (AC equivalent to Thevenin) with all RA s and RB s parallel to the ground. So it is sufficient that the parallel combination of RA s and RB s equals the characteristic ZO resistance of the transmission line, for the avoidance of reflections:

ZO = ( RA * RB ) / ( RA + RB )

To find the RA and RB values, the desired VT voltage is first selected at the point between the resistances and then, the previous formula is used with the next formula:

VT = ( V+ * RB ) / ( RA + RB )

Which gives the VT voltage as a function of the voltage divider formed by RA and RB. As in the case of parallel shutdown, special attention is required in selecting the VT so as not to violate VOL(max), and VOH(min).

The RA and RB resistors assist the drive circuit in generating the logic stresses at the input of the load. Through RA, current is provided to produce the high pullup, while RB calculates current, helping to produce pulldown. For this reason, Thevenin termination is used when the drive circuit is unable to produce strong logical output levels.

The choice of Rs and Rs (and Vs) depends on the driving ability (often asymmetric) of the output stage in the two logical states. Most logic families have difficulty producing a high logic level. For this reason VT is selected close to the high logic level, facilitating the work of the output stages.

Enhancing the digital signal through the combination of RA and RB produces clearer pulses at the input of the load and limits the instantaneous overvoltages of the logic voltages higher than the supply voltage and lower than the ground. Cleaner pulses improve the noise circle of the driven circuit. Through VT, it is also possible to adjust the rise and fall times of the signal: for example, a higher VT implies a faster signal rise time.

The biggest disadvantage of the Thevenin shutdown is the continuous flow of current from the grounding voltage, regardless of the logic level of the signal. In addition, resistors with exact proportions are required as well as additional interconnections of these resistors to the supply and ground voltage.

An additional problem arises when a VT is selected in the middle of the high and low level difference: if the transmission line is left unmanned and the driven circuit is CMOS, an input voltage close to the threshold level significantly increases its power consumption.

In Figures 5-9a and 5-9b it is clear that parallel termination is in fact a case of the Thevenin termination, where the RA is removed. By the same logic, a line can only be terminated at the supply voltage - or high logic level when it is less than the supply voltage - by omitting RB. The high-voltage parallel-ending method is applied to drive channels with open collector output stages.

Figure 5-10

Parallel ending of a transmission line, as well as Thevenin termination, have the main drawback of increased power consumption. Figure 5-10a depicts a termination variation ("AC termination") where the addition of a capacitor C prevents continuous current flow and reduces power consumption.

When the signal level changes, capacitor C acts as a short circuit, thus is "displaying" resistor R, which equals the characteristic line resistance ZO. As long as the digital signal is in a steady state, C equals an open circuit, thus preventing power consumption on R.

It should be emphasized, however, that while at low operating frequencies, the AC termination shows lower power consumption than the parallel and Thevenin termination, the difference is greatly reduced as the signal frequency increases.

The choice of capacitor C is crucial for the proper operation of the AC termination: low value capacitors amplify signal ripple, while large capacity values ​​increase the power required for charging and discharging. Usually the capacitor C is selected in such a way that the RC time constant of the circuit is greater than the round-trip delay and the return time of the signal.

AC termination requires more additional data to implement it. Also, charging and discharging C depends on many factors such as the frequency and duty cycle of the signal as well as the bit pattern. For example, a prolonged sequence of similar bits will charge C to the maximum, so it will take longer than normal to display the first counter bit.

Completing the presentation of the load-side termination methods, Schottky diodes are shown in Figure 5-10b. This termination method is different from the previous ones, because it does not attempt to match the characteristic ZO resistance of the transmission line.

The Schottky diodes run when the voltage range exceeds the supply or ground limits by an amount equal to the voltage drop of the diodes, leading to additional power to the feed lines. Unlike previous termination methods, the reflections on the transmission line are not completely avoided. The response characteristics of the diodes must be fast enough to be able to operate at high signal frequencies.

As mentioned earlier, Schottky termination does not depend on the characteristic ZO of the transmission line. For this reason, it is used when the ZO value is unknown, or when many capacitive loads are connected to the line, which reduce the final value of the line impedance. Schottky termination can be used at any point where reflections are present and consumes much lower power than parallel ending.

However, the most important advantage of the diode termination method is that most logic families have built-in Schottky diodes to limit off-state voltage clamp diodes. This does not require additional data to terminate transmission lines by this method.

## Termination at Source Signal Side

A different termination method, called series termination or back-matching, is implemented by adding a RS resistor at the start of the transmission line at the output of the drive circuit (Figure 5-11).

Figure 5-11

The resistor RS is selected using the formula: RO + RS = ZO

Where RO is the output impedance of the drive circuit and ZO is the transmission line characteristic resistance. With standard ZO = 50-75Ω, and RO = 10-60Ω, a typical RS value is 33Ω.

If the new logic level is VO, the initial amplitude of the pulse at point A (VA0) is determined by the voltage divider formed by RO, RS and ZO:

VA0 = ( ZO * V) / ( ( RO + R) + ZO )

And has half the value of VO. The signal traverses the transmission line at tPD time reaching point B. The reflectance factor ρB is about 1 because the load input impedance has a very high value (MΩ) relative to ZO. The signal width is immediately doubled to point B (it gets the VO value).

At the same time, a reflection front of size ½ VO returns to point A, where it will reach 2 * tPD from the start time of the signal. At point A, the signal range will get the VO value, but there will be no further reflections because the reflectance ρA is equal to 0 (RO + RS = ZO).

The serial termination method is often used to terminate point-to-point interconnections and shows the lowest power consumption of all previous termination methods because there is no continuous stream flow to the feed lines. In addition, no other impedance is added between the signal line and the ground. It is especially suited for interfacing CMOS circuits, which have almost zero input current. Ending address rows and memory control is the typical example of using this method.

Ending in a series also has some drawbacks. The value of RO is usually different for each logic state and shows deviations from circuit to circuit, and it is also dependent on temperature. For this reason, the selection of the RS stop resistance is approximated and not with absolute precision. Reflection coefficient pA is not exactly equal to 0 and thus multiple reflections are not totally excluded, they are simply minimized.

Successful end-to-end operation is based on the first reflecting front to obtain the correct logic level across the line. This practically means that each point on the line acquires the correct logical level at a different time, depending on the delay of the first reflection face.

If other loads (entrances) are connected along the line, there is always the risk of non-simultaneous logical transitions. In addition, the capacities of the additional loads change the characteristics of the reflecting face, making it unpredictable to change the signal level. For the above reasons, end-to-end use is only used when the load is concentrated at the end of the transmission line.

## Summary of Use of the Different Termination Methods

Table 5-3 below summarizes the proposed uses of the different termination methods when required, by the transmission line length:

 Case Termination Method TTL and CMOS with strong driving ability Parallel (either to ground or to the supply voltage) TTL and CMOS weak driving ability Thevenin (precipitate or provides current, aiding driving) CMOS Interface (point to point) In series FACT (advanced CMOS) in low power applications In series (restricts power consumption) FAST (advanced Schottky TTL) Thevenin (helps the limited current supply capability) cache memory / SDRAM arrays In series Channels with a variable number of circuits with three-state outputs Schottky diodes (adaptation to different impedance values ​​of the channel) Driving lines with heavy load Thevenin (driving assistance) Low Power Systems In series, Schottky diodes, AC ECL Parallel (end voltage to -2.0V) Thevenin (avoiding the use of -2.0V, but the power consumption is 8 times greater than that of the parallel) In series

Table 5-3