Digital Signal Integrity Tutorial (page 4)



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⚛ Noise Output Levels ⚛ Problems Caused by Ground Bounce ⚛ Termination of transmission lines ⚛ Driving Interconnecting Channels ⚛ Interaction of Signals (Crosstalk)
⚛ Peak Totem-Pole Current (Crossover Current) ⚛ Ground Bounce Noise Troubleshooting ⚛ Termination Method on the Load Side ⚛ Distributed Channel Line Capacity ⚛ Differential Signal Transmission
⚛ Charging Current/Discharge Capacity Output ⚛ Signal Loopback ⚛ Termination at Source Signal Side ⚛ Termination of Channel Lines ⚛ Evolution of Differential Transmission Technologies
⚛ Ground Bounce ⚛ Transmission Lines ⚛ Summary of Use of the Different Termination Methods ⚛ Logical Interconnection and Bus Drivers Families  



Driving Interconnecting Channels

In modern digital systems, most of the system logic is now integrated into a limited number of high density integrated circuits. In the same way the discrete gate-to-gate interconnections "disappear" within the integrated circuits. Only interconnection buses, common signal arrays, interconnecting multiple subsystems remain on the surface of the printed circuit boards. Interconnecting integrated circuits in a bus also requires special rational families with increased driving capability: buffers, registers and latches, multiplexers, and level shifters.

Subsystem Interface Busses


Figure 5-12


Figure 5-12 illustrates the typical structure of a digital system, consisting of several subsystems and a common interconnect. This bus is implemented on a printed backplane. Along the channel, there are connectors of the sub-system boards. The logic circuits of each subsystem, are connected to the common bus through dedicated I/O circuits (transceivers).

The advantages of organizing into subsystems are:


  • A) The base plate including the interconnector is designed with optimized features, with provision for the maximum loads that are likely to be associated with it. In high-speed designs, the baseplate is always multi-level and has uniform features for all channel conductors. Thus, the transmission lines formed have predictable characteristic resistance values ​​and signal propagation delay.
  • B) on the sub-system side, the special transceivers isolate the remaining logic circuits of the subsystem from the bus, limiting the size of the capacitive load added to the transmission lines of the bus. The drive circuits are placed as close as possible to the connector to minimize parasitic capacitance.



Distributed Channel Line Capacity

For the study of channel behavior as transmission lines, the simple model of a driving-load circuit is not enough. On each line of the ZO resistive channel, the different capacitive loads of the subsystems are added at equal points (Figure 5-13).

Data transmission on a data channel


Figure 5-13


The number of subsystems connected to the bus is not always the same, nor are the connection locations. During operation, some interface sockets may be free. The design must take into account the worst case when the maximum number of subsystems is connected to the bus.

Adding a subsystem is equivalent to adding a CL capacitive load to the channel lines. This load consists of the individual capacities: the conductor connecting the bus to the interface socket (~ 1pF), the interface socket itself (~ 1pF), the conductor on the sub-system board until the isolation circuit (~ 2pF) and the Input/output capacity of the isolation circuit (7-10pF).

When the subsystems are evenly distributed over the total length of the channel, dividing the total capacity of all subsystems with the channel length, that way is calculated as the distributed CD capacity per unit length.

The size of the distributed CD capacity is added to the capacity per unit length CO of the transmission line and affects the final value of the impedance (ZO(eff)) and the transmission delay (tP(eff)) of the line:


ZO(eff) = ZO /  (1 + (CD / CO))


TP(eff) = tP *  (1 + (CD / CO))


From the previous relationships it appears that with the increase of the CD the line impedance decreases while the propagation delay of the signal is increased. The smaller the ZO(eff), the more current is required by the drive circuit for transmitting the signal.

The following table 5-4 gives a real example of how ZO(eff) and tP(eff) vary from a single conductor (without interface sockets) to a bus without full load.



Simple Conductor on a PCB

Bus Conductor unladen

Bus Conductor Full Load

Inductance LO

6.5 nH/cm

6.5 nH/cm

6.5 nH/cm

Capacitance CO

0.4 pF/cm

0.4 pF/cm

0.4 pF/cm







<< 1pF

<< 1pF




~ 1pF

Input Capacity Buffer




Distributed Capacitance CD

0.4 pF / cm

1.2p F/cm

4.73 pF/cm

Final Impedance ZO(eff)




Final Propagation Delay tP(eff)

5.1 ns/m

8.8 ns/m

17.5 ns/m


Table 5-4



Termination of Channel Lines

The interconnection channel lines must be terminated, like any kind of conductor, to avoid reflections and incorrect transmission of the digital signal. The channels on the base boards are up to half a meter long, making it necessary to terminate them.

Termination of channel paths is implemented by adding resistances at both ends of the line, the parallel combination of which matches the impedance ZO(eff). Alternatively, other elements such as the Schottky diodes are added, whereas the end-of-line method (the source of the signal) can not be used because the drive circuit is not at the end of the transmission line.

As can be seen from Table 5-4 of the previous paragraph, calculating the termination resistors is particularly difficult because the final impedance ZO(eff) varies depending on the number of connected loads on the line. The choice of the termination resistors so that their parallel combination matches the characteristic resistance ZO is unsatisfactory when the final impedance of the ZO(eff) line impedance has a much lower value. In this case, smaller terminating resistors are selected to match the full load ZO(eff) of the bus.

The most common method of terminating channel lines is parallel termination to the supply voltage, with two resistors equal to the ZO(eff) of the channel at both ends (Figure 5-13). This method is particularly useful when the drive circuits have open collector outputs, whereby the terminating resistors are also used to raise the line to the high logic level.

It should be noted that when the bus lines are terminated at both ends then the driving circuit must provide or precipitate the double amount of current from the termination with a single resistor. By matching the termination resistors with the full load bus ZO(eff), it often requires the use of resistors with a low value of up to 20Ω. In this case, the required driving current is particularly high (≥100mA per pin) and beyond the capabilities of common digital circuits.

Another reason why it is desirable to use circuits with increased driving capability is to drive the loads with the incident wave switching.

As in the case of point-to-point lines, as in the case of channel lines, the original voltage front at the output of the drive circuit depends on the relationship of the output impedance RO of the drive circuit and the Characteristic ZO(eff) of the channel. If the range of the original voltage is greater than the VTH threshold voltage of the driven inputs then the change in the logic state of the driven circuits will occur when the first front of the signal is propagated to the line, requiring the minimum delay time. Otherwise, it will take the return time of the reflected voltages to get all the points on the line the desired value.

In order to achieve the driving of the loads with the primary front of the signal, RO should be the smallest possible (which in practice means that the driving circuit provides an increased amount of current), while ZO(eff) should be kept as high as possible .

Driving with the primary front is the fastest but has increased power consumption. For this reason, some channel systems, such as the PCI specification, benefit from signal reflections to achieve the final level of the signal with lower energy consumption ("green systems").



Logical Interconnection and Bus Drivers Families

The digital drive circuits of the interconnection channel lines are interposed between the system logic circuits and the interface bus, as shown in Figure 5-5-14. The interface side with the other logical circuits is called A-port, while the interconnection with the bus lines is via the B-port. The two sides of the interface usually have different design, logic levels and driving capability.

Digital Interface Circuits


Figure 5-14


Logic families of digital universal circuits are unable to meet the specific characteristics required by the interconnection circuits. For this reason, special logical interfaces (interface logic) have been designed. The desirable features of logic interconnection families are described below:


  • A) The propagation delay of the signal through the interconnection circuits must be the minimum possible, irrespective of the number of bits that change at the same time. The short propagation delay allows for maximum channel frequency. The fastest interconnection lines of the trade achieve a minimum 2ns propagation delay.
  • B) B-port bus circuits must have increased driving capability to successfully drive the bus even when full load is connected to the bus. The supplied current depending on the interface family may exceed 100mA per lead for driving lines with a typical impedance of up to 20Ω.
  • C) driving the bus lines must be done with minimal noise and reflection. For this reason, the drive circuits have slew-rate control and limitation devices to avoid logic hopping.
  • D) Minimum power should be used to drive the bus. This is achieved by reducing the logical channels on the channel side. Modern driving circuits use logic levels on the channel side with a range of 1V, and adjust the threshold voltage to within ± 75mV.
  • E) On the interface side with the other logic circuits it is possible to connect integrated circuits with supply voltages from 5V to 3.3V, or even lower.
  • F) Modern interconnection circuits have special pre-charging devices which allow the insertion or removal of subsystem PCBs during operation (live insertion - figure 5-15).

Input of subsystem during operation


Figure 5-15


The different length contacts allow for the provision of an auxiliary voltage (BIAS VCC) to the output terminals before they come in contact with the bus connector. The presence of this voltage prevents charging/discharging sparks on the bus lines at the time of connection of the outputs. The process is completed by providing the normal supply voltage, which interrupts the auxiliary voltage and restores the normal operation of the circuit.

The addition and removal of subsystem boards during operation is necessary in many control or telecommunication systems, where e.g. It is not possible to shut down completely to replace or maintain subsystems that have failed.

Summarizing the properties of modern logic family interfaces, they are presented in Table 5-5 that follows the features of the GTLP (Gunning Transceiver Logic Plus) family of CMOS technology:



Logic Levels


Transistors - Input/Output


Driving Ability

± 24mA


Logic Levels

LOW: 0.55V HIGH: 1.5V

Threshold Voltage

1.0V ± 50mV

Transistor Output

CMOS open drain

Driving Ability

100mA @ 0.55V

Input/Output Capacity

10.5 pF (max)

Rate of climb/descent signal

0.5 / 0.43 V / ns

V BIAS CC (live insertion)

0.95 V - 1.05V





0.65-m CMOS



power consumption


propagation delay (max)

A -> B: 7.7 or 6.3 ns B -> A: 5.5ns


Table 5-5



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