Digital Signal Integrity Tutorial

  

 

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⚛ Noise Output Levels ⚛ Problems Caused by Ground Bounce ⚛ Termination of transmission lines ⚛ Driving Interconnecting Channels ⚛ Interaction of Signals (Crosstalk)
⚛ Peak Totem-Pole Current (Crossover Current) ⚛ Ground Bounce Noise Troubleshooting ⚛ Termination Method on the Load Side ⚛ Distributed Channel Line Capacity ⚛ Differential Signal Transmission
⚛ Charging Current/Discharge Capacity Output ⚛ Signal Loopback ⚛ Termination at Source Signal Side ⚛ Termination of Channel Lines ⚛ Evolution of Differential Transmission Technologies
⚛ Ground Bounce ⚛ Transmission Lines ⚛ Summary of Use of the Different Termination Methods ⚛ Logical Interconnection and Bus Drivers Families  

 

Digital circuits usually operate in an environment with noise and electromagnetic interference. In addition, increasing the operating frequency of modern systems above 30MHz causes phenomena in the range of radio frequency (RF), converting the digital circuits in high noise sources. This noise occurs by coupling on transmission lines and reduces the quality of the digital signals, causing operating errors.

The digital signal is vulnerable to noise during its transmission (figure 5.1) between different integrated circuit on the same printed circuit (1), between the subsystems and the base boards (2) between subsystems of the same system (3) and between different systems (4). To cover longer distances, the digital signal is transmitted over networks using a modulation method.

Various forms of interconnection

 

Figure 5-1

 

Maintaining the integrity of digital signals during their transmission are vital to the safe operation of systems. This chapter analyzes the main causes of noise generation in modern digital circuits and presented the ways to address them.

In signal transmission between integrated circuits, special role played by the noise generated by the changes of reasonable charges. This noise is due to the current flow to and from the driven circuits and can affect the levels of transmitted signals.

As the speed of digital circuitry increases, occur in signal transmission conductors "analog" phenomena as the voltage fronts reflections. These reflections can cause oscillation of logical channels and erroneous signal reception.

In modern digital systems important role played by families logical interconnection of the various subsystems through common channels. For driving the interconnecting channels of digital circuits required by particular characteristics.

We will study the effect of the interaction of adjacent signal conductors. This interaction is due to parasitic capacitive and inductive coupling and is a major cause of noise occurrence.

Finally, in the last Section we will discuss the basic principles of differential transmission through a pair of identical but opposite polarity signals. The differential transmission has high immunity to noise and is suitable for long pipelines.

 

 

Noise Output Levels

In any digital circuit, the output stages (driving) play the main role in signal transmission in subsequent circuits. Unlike the remainder of the internal logic of the integrated circuit, the output stages are required to have a special ability to supply or power absorption in a very short time, so it can successfully lead its related to these loads.

The rate of switching of currents in output levels increases as they grow speeds of modern digital circuits. At high operating frequencies abrupt changes of current flowing through the output stage causes the noise impression.

In the next paragraphs we will see the causes of this generating current flow, which causes the noise mechanism and ways to counter it.

 

 

Peak Totem-Pole Current (Crossover Current)

Figure 5.2 shows a typical CMOS output stage. The two transistors (pMOS and nMOS) are connecting the output of either the supply line (V+), or to ground (GND), as the output value. Almost the same happen to the output stage circuit with a bipolar junction transistor.

Totem pole current peak

 

Figure 5-2

 

When changing the output value from one state to another, there is a short period during which both transistors conduct. The direct effect is the occurrence of a leakage current peak (IS) directly from the supply voltage to ground. This current is commonly called totem-pole current, because it is characteristic of steps transistor pair in totem-pole configuration.

As shown in Figure 5-2, the pick of the totem-pole power occurs about in the middle of the transition of the output voltage from one logic state to another.

 

 

Charging Current/Discharge Capacity Output

In addition to the totem-pole current peak when switching an output from one logic state to another, the output stage flows through the charging or discharging internal and external capacitances. The internal capacitance is formed in the same output stage, while the external capacitance comes from the capacitive loads of the inputs of driven circuits which are connected to the output stage (every digital input presents capacitance of 2pF to 10pF depending on the technology used). Figure 5-3 This capacity symbolically illustrated as a capacitor CL.

Charging Discharging Current of Output Capacitances

 

Figure 5-3

 

When switching the output from the low to the high logic level (Figure 5-3a) the capacitance CL is charged by the voltage V+. The opposite happens in the case of transition from the high to the low logic level: the capacitance CL is discharged through the ground. The amount of current flowing through the output stage is given by the formula:

 

ΙCL = CL ( dV / dt )

 

where dV is the voltage difference between high and low logic level. From this relationship it appears that the charge / discharge current of the capacitance is proportional to the difference in the logic level HIGH and LOW (voltage swing) and the speed change of the output voltage (dt term minimization).

 

 

Ground Bounce

Both the current required for charging or discharging of the output capacitances, and the totem-pole current, both flow through the ground and power terminals. These terminals, as all input and output terminals of an integrated circuit exhibit parasitic inductance between the inner silica surface (die) and the package (package). Each input/output of the silicon surface is connected via a conductor (wire) in an inner frame and this in turn is connected to the external terminals. Each portion of the interface, presents a certain inductance value. Each package type has a different value of inductance for each terminal, as shown in Table 1.5:

 

Packing

Inductance per terminal

PDIP

13.7nH

PLCC

10nH

SOIC

8.5 nH

QSOP

3.6nH

FC-BGA

1nH

 

Table 5-1

 

Parasitic inductance is also shown in the circuit lines (PCB), which connect the terminals of the integrated circuit with the central power source. In Figure 4.5 the internal inductance denoted as LCHIP, while the inductance of the circuit as LPCB.

Grounding bounce

 

Figure 5.4

 

In the example of Figure 5-4, as a logical output changes state from HIGH to LOW, a current amount is flowing to the terminal of the ground GND. This current stream results in the development of a potential (V) to the parasitic inductances LCHIP and  LPCB according to the formula:

 

V = L ( dI / dt)

 

This potential temporarily increases the internal voltage GND to the silicon surface to a level greater than 0V. As soon as the current flow is reduced, then is followed by a corrugation of the internal GND to the stabilization.

This phenomenon is called ground bounce (ground bounce) and can cause errors in the operation of digital circuits. The potential difference in modern high speed circuits may exceed 1V.

Correspondingly as the ground bounce occurs, a proportional voltage change happens at the internal supply voltage (VCC). But because most logic families use as a reference voltage the ground and have greater tolerances with respect to the logic high level, in this case the bounce VCC considered minor.

The ground bounce is particularly strong when simultaneously are changing multiple outputs of the same integrated circuit, because it multiplies the magnitude of the current flowing to/from the ground/power terminals. For this reason, the noise generated is often called (simultaneous switching noise - SSN). The simultaneous change of logic outputs, is the main characteristic of digital systems which are clocked via a central clock pulse. A typical example of simultaneous outputs switching in microcontroller systems is the change of memory address from 0FFFF (hex) to 10000 (hex).

 

 

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