Interconnection and Timing of Digital Circuits Tutorial (page 2) 

Page 1  At this page (2) 
⚛ Interconnection of Digital Circuits  ⚛ Timing of digital circuits 
⚛ Basic Principles of Interconnection  ⚛ Timing circuits with logic gates 
⚛ Interconnection of Different Logic families  ⚛ Crystal oscillators 
⚛ Interfacing TTL and CMOS circuits  ⚛ Integrated oscillators 
⚛ Switching Low Voltage CMOS Circuits  
⚛ Interconnection of TTL / CMOS and ECL Circuits  
⚛ Open Collector Output Connections 
Timing of digital circuits
The operation of digital circuits is clocked with one or more clocks. These signals are crucial for the proper operation of digital systems, especially in the case of high frequency operating circuits. The following paragraphs show various forms of timing, low and high precision circuits.
4.2.1 Timing circuits with logic gates.
By combining logic gates, R and C components, it is possible to synthesize timing circuits for systems that do not require large operating frequencies and high timing accuracy.
Figure 43
The circuit of Figure 43 is a monostable multivibrator (oneshot): the circuit is in a steady state, and for a short time it can be in an unstable state before returning to its original equilibrium state. The circuit consists of two CMOS gates (NOR and inverter) and the elements R and C. The circuit operation is as follows:
In time t = 0 the input voltage V_{P} = 0, the voltage V_{2} = V_{CC} and the output voltage V_{o} = 0. Therefore the voltage V_{1} at the output of the NOR gate is high and the circuit is in equilibrium mode.
In time t_{i} the V_{P} input goes into high state for a short time. V_{1} switches to low state and momentarily the same happens with V_{2}, because capacitor C keeps the voltage previously existing on its terminals (0V). Thus V_{o} output goes to high (HIGH).
But then, C is exponentially charged by resistance R and V_{2} approaches the inverter's V_{T} threshold voltage in time:
T = RC·ln(V_{CC}/(V_{CC}  V_{T}))
At that moment, V_{o} becomes '0' and, since V_{P} has already returned to a low state, V_{1} becomes HIGH. As capacitor C is charged at V_{T} voltage, V_{2} momentarily follows the change by overcoming the V_{CC} until the D protectors at the input of the inverter begin to convert to V_{CC} + V_{D} voltage. V_{2} then returns exponentially to the V_{CC} value.
The accuracy of the pulses produced by the circuit of Figure 43 is not high, because it depends on the values of V_{T}, R and C, which have variations and tolerances for each component. The activation pulse at the V_{P} should be greater than the propagation delay of the two gates so that '1' can return to the NOR input for pulse maintenance.
Figure 44
Figure 44 illustrates a circuit with two CMOS inverters, the output of which continuously switches over at fixed intervals from one logic state to the other. This circuit is called "astable multivibrator" or oscillator.
Assume that at time t = 0, the V_{1} exceeds the threshold voltage V_{T} of the first inverter. Then V_{2} becomes '0' and V_{o} output is '1' (V_{CC}). Through capacitor C, this change returns to V_{1}, which obtains instantaneous the value of V_{CC} + V_{T}.
Then C is discharged via R to V_{2} (which is '0') and voltage V_{1} drops. When V_{1} becomes less than V_{T}, V_{2} becomes '1' and V_{o} output goes low. The output change affects V_{1}, which is instantly decreasing by V_{CC} and acquires the V_{T}V_{CC} value. The return time of V_{1} at the threshold voltage is equal to:
T1 = RC·ln((V_{CC}+V_{T}) / V_{T})
Then, C is charged by R from V2 (now it is in high state) and voltage V1 is increasing. When V1 reaches the VT again, V2 becomes '0' again and Vo becomes '1'. The circuit continuously repeats the oscillation. The time required to reach V1 the threshold voltage is:
T2 = RC·ln( V_{T } 2V_{CC }/ V_{T}  V_{CC })
In circuit analysis of Figure 44, the influence of input protection diodes of the first inverter must also be taken into account: in fact V_{1} ranges between V_{CC} + V_{D} and V_{D}.
The two times T1 and T2 are equal when the threshold voltage equals V_{CC} / 2. In each case, the period of the generated clock signal is equal to the sum of these two times.
4.2.2 Crystal oscillators.
The circuit of the previous paragraph can produce simple lowprecision clock and 1MHz clock waveforms. Higherfrequency clock signals are produced using crystal oscillators.
Before analyzing the circuit of a crystal oscillator, some theoretical elements for the operation of an oscillator and the physical properties of the quartz crystals are listed below.
Figure 45
An oscillator consists in its theoretical form of an amplifier circuit and a filter, which are connected to a positive feedback loop (Figure 45). To operate the circuit as an oscillator,
 a) the gain in the loop must be greater than one.
 b) the total phase shift of the signal to be multiples of 2π.
In Figure 45 the amplifier reverses the signal by shifting the phase by 180^{o} while the filter still adds 180^{o} for a total phase shift of 360^{o}. The amplifier also provides the required gain (>1) to amplify the signal to a steady state, Where the gain is 1.
The filter determines the operating frequency of the oscillator and provides a coupling between the output and the input of the amplifier. Discrete elements L and C can be used to implement the filter, but a quartz crystal is usually used for this purpose.
Quartz is piezoelectric. This means that when an electric field is applied to it, a physical shift (oscillation) of the material occurs, and vice versa. The quartz crystals are processed into thin sections and have a very stable primary oscillation frequency depending on their cutting. It is possible to make crystals with oscillation frequency up to 40MHz, while frequencies up to 300MHz use higher harmonic oscillations.
A quartz crystal is described by the equivalent circuit of Figure 46 and oscillates at two major frequencies:
 A) At the coordination frequency in series, C_{1} and L_{1} are tuned in such a way that the crystal resembles a small resistor R_{1}.
 B) At the parallel resonance frequency, the combination of L_{1} and C_{1} is inductive and coordinated with C_{o}.
Figure 46
The two frequencies differ by about 0.1%. The crystals are constructed to operate in one of two modes of tuning. Constructively, there is no difference between the two types, just the nominal oscillation frequency of the crystal differs. In addition, for the parallel tuning, the required external load CL is determined for oscillation exactly at the indicated frequency.
In the circuit of Figure 47 with a CMOS inverter, the circuit operates in parallel resonance. Thus it behaves as an inductive element and together with the capacitors C_{1} and C_{2} it shifts the signal by 180^{o}. C_{1} and C_{2} represent the capacitive load of the crystal and usually have a similar value.
Figure 47
Resistor R_{1} holds the inverter in the active operating range (between '0' and '1'), while R_{2} isolates the inverter output from the crystal network, allowing a cleaner output waveform to be produced.
The CMOS inverter provides the first 180^{o} phase shift of the signal phase in the feedback loop and at the same time amplifies the signal (the gain of such an inverter in the active region is greater than 10). The circuit begins to oscillate with the influence of the ambient electrical noise and the signal is successively amplified until the oscillator enters a steady state. In this final state, the oscillation is selfsustaining at a frequency equal to the frequency of parallel crystal tuning.
4.2.3 Integrated oscillators.
In modern highfrequency digital circuits, integrated crystalline oscillator circuits are used in sealed metal packages instead of discrete circuitry such as the one in the previous paragraph. The accuracy of integrated oscillators is crucial for the required timing of digital systems and must be carefully selected based on their functional characteristics.
The main parameters that characterize an integrated oscillator are:
 • The rated operating frequency (MHz)
 • Operating mode (tuning type)
 • Stability of oscillation (percentage of divergence)
 • Frequency shift with "aging" (deviation per year)
 • Operating conditions (temperature, power, load, etc.)
 • The type of signal produced (TTL, CMOS or ECL levels)