Interconnection and Timing of Digital Circuits Tutorial
|At this page (1)||Page 2|
|⚛ Interconnection of Digital Circuits||⚛ Timing of digital circuits|
|⚛ Basic Principles of Interconnection||⚛ Timing circuits with logic gates|
|⚛ Interconnection of Different Logic families||⚛ Crystal oscillators|
|⚛ Interfacing TTL and CMOS circuits||⚛ Integrated oscillators|
|⚛ Switching Low Voltage CMOS Circuits|
|⚛ Interconnection of TTL / CMOS and ECL Circuits|
|⚛ Open Collector Output Connections|
Interconnection of Digital Circuits
When designing a digital system, the need for mixing logic circuits of different technologies and functional characteristics often arises. For the secure interconnection of these circuits, their functional characteristics are taken into account and additional conversion circuits are introduced where necessary. The following paragraphs describe various point-to-point logic circuits (from the output of the drive circuit to the driven inputs) as well as common channels with open collector outputs.
Basic Principles of Interconnection
The possibility of interconnecting two or more digital circuits, with the output of one leading the entrances of the others, depends on their electrical characteristics. In order for the interconnection to be successful, certain conditions should apply:
A. Compatible Logic Levels: The output of the drive circuit should produce reasonable levels compatible with the input levels of the driven circuits. If interconnected digital circuits belong to the same logic family they will have compatible logic levels. But in the case of circuit interconnection from different logic families it should be investigated whether it is assured that (assuming that circuit A leads to B):
VBIH(max) > VΑOH(min) > VBIH(min)
VBIL(min) < VΑOL(max) < VBIL(max)
If the above relationships are marginal, there is a possibility that the high and low status noise margins (NMH = VAOH(min) -VBIH(min) and NML = VBIL(max) -VAOL(max) to be very small. In this case, the maximum expected noise level in the system should be calculated. If the expected noise is greater than the noise margins, then the interconnection will be unsafe.
B. Sufficient driving capacity (fanout): The drive circuit should provide or precipitate a sufficient amount of current to meet the needs of the driven inputs. Assuming that the output leads (n) entrances with similar characteristics, it should apply:
| IOL(max) ≥ | n · IIL(max) and IOH(max) ≥ | n · IIH(max)
If the leading output is unable to meet the needs of the inputs in a supplied supply, there is a risk that the logic states will be corrupted, resulting in logic errors.
C. Safe up-down time of the signal: Different logic families define a maximum time (or minimum Δt / ΔV rate) for passing the signal at the circuit inputs from one logic level to the other. Failure to observe this time, with very slow signal transitions, may result in malfunction of digital circuits.
As mentioned before, the parasitic capacities of the driven inputs (CL) together with the output impedance (RO) of the drive circuit form an RC circuit, delays the signal transition during the change of state. For transition of the signal from 10% to 90% of the total transition range a time T10% -90% is required:
T10% -90% = 2.2 · RO · CL
In any case of digital circuit interconnection, it must be ensured that the signal transition is achieved within the time allowed.
Interconnection of Different Logic families
This section describes the methods of interconnecting integrated circuits belonging to logic families of different technologies. In some cases, it is possible to interface directly, but in others, additional circuits need to be used to convert logic states.
Interfacing TTL and CMOS circuits
Figure 4-1a illustrates the logic input / output levels of the TTL and CMOS integrated circuits with VCC = 5V. As can be seen, a CMOS circuit can directly lead a TTL input because the CMOS output levels are compatible with the TTL input levels.
The maximum number of TTL inputs that can be output from a CMOS output is limited by the output power of this output. The leading output capacity depends on the logic CMOS family: for example, with a maximum IOL(max) = 4mA, a 74HC logic output can drive up to 10 inputs LSTTL (IIL(max)LSTTL = -0.4mA) .
In the same figure 4-1a it appears that direct driving of CMOS inputs from a TTL output is not possible due to the inconsistency of the logic states (VOH(min)TTL < VIH(min)CMOS). So in this case there are two options:
A) Addition of RP resistance (pullup - figure 4-1b): This resistance improves the high output level of the TTL circuit. The RP resistance value adjusts the power consumption to it when the output is in low state while simultaneously affecting the output transition speed to high.
In low mode, the TTL output drains current from the VCC via the RP and from the entrances of the gates. The RP value should be such that the VP output voltage does not exceed the VOL(max)TTL. Assuming that the TTL output leads (n) CMOS inputs and symbolizing the current through RP as IR, it is:
VP = VCC – RP · IR = VCC - RP · (IOL(max)TTL - n · | IIL(max)CMOS | ) ≤ VOL(max)TTL
Where the minimum RP value is shown:
RP(min) = (VCC - VOL(max)TTL ) / (IOL(max)TTL + n · IIL(max)CMOS)
The maximum RP value can be calculated when the output is in high mode. In this case, the output voltage VP should not be lower than the VIH(min) CMOS. This logic level is much higher than the standard TTL output value. Thus, the TTL output, after fast moving to about 2.7V, is then cut off and all current to the CMOS inputs comes through RP:
VP = VCC - RP · IR = VCC - RP · (n · | IIΗ(max)CMOS | ) ≤ VIΗ(min)CMOS
Where the maximum RP value occurs:
RP(max) = ( VCC – VIH(min)CMOS ) / ( n · IIH(max)CMOS )
The maximum value of RP is significantly limited by the maximum allowed transition time of the signal at inputs of CMOS circuits. The RP, together with the input capacities of the guided gates (Ci), form an RC circuit whose time constant determines the signal transition rate from low to high. For transition of the signal from 10% to 90% of the total transition range a time T10% -90% is required:
T10% -90% = 2.2 · RP · (n · Ci)
Using the 10% -90% maximum migration time given in data sheets, it is possible to find the maximum allowed RP, the value of which is significantly lower than the previously calculated RP(max).
B) Using an integrated CMOS circuit with inputs compatible with TTL levels most logic CMOS families include circuit variants that have modified the geometry of the input transistors appropriately so as to reduce the threshold voltage. This modification allows the inputs to be driven by TTL circuits. These circuits are represented by the addition of a "T" in the name of the logic family, e.g. 74HCT or 74ACT.
Switching Low Voltage CMOS Circuits
When switching CMOS technology to lower power voltages, interconnection of integrated circuits of different supply voltages is often required.
In any case, a higher power supply CMOS circuit can directly lead to a second lower supply voltage, because the logic levels are compatible. The only prerequisite is that the driven input has a tolerance at overvoltages greater than the VCC of the driven circuit. This property is ensured in most of the newest CMOS logic families.
Otherwise, when a lower voltage supply CMOS circuit has to lead another with a higher VCC, direct interconnection is not possible due to the inconsistency of the logic states. In this case special integrated logic conversion circuits must be used. These circuits have dual voltage supply terminals.
Interconnection of TTL / CMOS and ECL Circuits
The TTL and ECL output input logic levels are incompatible, whether used for ECL VEE = -5.2V or VEE = 0V (PECL). For the interface, special integrated conversion circuits of logic states, which are powered by double voltage (+ 5V, -5V) for ECL / TTL conversion, or only + 5V in the case of PECL / TTL interface, are used for the interconnection. For driving CMOS inputs, an ECL / TTL converter is usually used and then CMOS inputs compatible with TTL levels (74HCT / ACT).
Open Collector Output Connections
Figure 4-2 illustrates the (n) open collector outputs in a common line and the inputs (m) of other logic gates:
The open collector outputs of the figure require the connection of a RP rising resistor to generate the high logic level. The calculation of this resistance is given below.
A) For the common line to be in high mode, all open collector outputs must be in high mode (at cut-off). In this case, current through RP flows to the entrances of the gates (m · IIH(max)), but also to the open collector outputs (n · IOH (max)). This IOH stream is essentially a leakage current, since the open collector outputs in high state are cut off. The value of RP should be such that VP ≥ VOH(min) and with VP = VCC - RP · IR = VCC - RP · (n · IOH(max) + m · IIH(max) we get the highest value of RP:
RP(max) = ( VCC - VOH(min) ) / ( n · IOH(max) + m · IIH(max) )
B) For a common line to be in a low state, only one open collector outlet is needed and should be in a low state. In this case, the current from the guided inputs and the one flowing through the RP is precipitated at those open collector outlets that are in a low state. The worst case of incurring charges occurs when only one of them is in a low state, so the minimum RP value is calculated in this case:
In the low state of the common line, VP ≤ VOL(max) and with VP = VCC - RP · IR = VCC - RP · ( IOL(max) + m · IIL(max)) should be the minimum RP:
RP(min) = ( VCC - VOL(max) ) / ( IOL(max) + m · IIL(max) )
RP is selected from the range between the maximum and the minimum allowable value. Smaller RP implies greater power consumption and faster line transition from low to high. In any case it should be considered whether the rise time of the resulting signal is within the specifications of the gates.