Digital Circuits with Bipolar Transistors Tutorial (page2)

  

 

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⚛ The bipolar contact transistor ⚛ Propagation Delay ⚛ ECL Basic Gate (OR / NOR)
⚛ Early digital logic circuits ⚛ Power consumption ⚛ ECL Transfer curve (OR & NOR)
⚛ Diode-transistor logic (DTL) ⚛ Unused Entrances / Gates ⚛ ECL Driving ability
⚛ DTL gate power ⚛ Various TTL logic gates ⚛ ECL Propagation Delay
⚛ Logic transistor-transistor (TTL) ⚛ Logic TTL families ⚛ ECL Power consumption
⚛ NAND TTL Gate Function ⚛ Schottky TTL logic gates ⚛ ECL Differential signal transmission
⚛ Standard TTL standard features ⚛ LS TTL logic gates ⚛ Use of Positive Feed (PECL)
⚛ Logic levels and noise margins ⚛ Advanced TTL Gates ⚛ Logic ECL families
⚛ Driving ability ⚛ Emitter Conjugate Logic (ECL)  

 

 

 

Propagation Delay

The propagation delay of a signal from the input to the output of a TTL gate determines its operating speed. For standard TTL circuits, the propagation delay is measured when the input and output signal is 1.5V.

In standard TTL circuits, the propagation delay for changing the low to high logic output (tPLH) is greater than the delay for changing the output from high to low (tPHL). This is because the transistor T3 enters deep into the saturation range when the output is in low state, so it slows further to return to the cut off when the output goes to high state.

Example: For a standard TTL NAND gate (7400) standard signal propagation delay values ​​are tPHL = 7ns and tPLH = 11ns, supply voltage VCC = 5V, ambient temperature TA = 25°C and output load capacity CL = 15pF.

For the calculation of an average propagation delay value (tPD), the ratio is used:

 

tPD = ( tPHL + tPLH ) / 2

 tPD = (7+11)/2  for the previous example 

 

And respectively the maximum operating frequency of the gate for a complete L-H-L cycle is given by:

 

f(max) = 1 / ( tPHL + tPLH )

f(max) = (7+11) ≈ 55MHz for the for the gate 7400 

 

The propagation delay decreases with the increase of the supply voltage and increases with the increase of the output load capacity. Also, the rise in temperature causes small deviations in the tPD value, which may be either positive or negative, depending on the gate's construction parameters.

 

 

Power Consumption

The static power consumption P (as long as the outputs are kept constant) of a TTL circuit is determined by the ICC power current consumed in the circuit:

 

P = VCC x ICC

 

For each TTL integrated circuit, two feed current values, ICCH and ICCL are given, depending on whether the gate of the circuit is at high or low logic level respectively. The ICCH stream is 2 to 3 times smaller than ICCL, e.g. For a NAND 7400 gate the following values ​​are given: ICCH(max) = 8mA and ICCL(max) = 22mA.

In the case where gate exits alternate reasonable levels, the average power consumption is calculated using the ICC average. For calculating the ICC mean value (av) by ICCH and ICCL, the ratio of the time at which the outputs are in high state to the time it is in the low duty cycle is taken into account. If this ratio is 50% (equal times at high and low output) then it is:

 

ICC(av) = ( ICCH + ICCL ) / 2

 

While for random reason r applies:

 

ICC(av) = (r) ICCH + (1-r) ICCL

 

In addition to static consumption, TTL circuits also display dynamic power consumption, due to the current peaks generated when changing the output status. These peak peaks approach the maximum possible IOS current and are due:

  1. (A) the current flowing momentarily between power supply and ground totem pole output stage when changing the output level; and
  2.  
  3. (B) the current required to charge / discharge the capacities of the loaded loads at the exit of the gate.
  4.  

Dynamic power consumption is proportional to the operating frequency. With a typical CL load of 50pF, the static power consumption of a TTL circuit is up to 1MHz. Higher operating frequencies show the effect of dynamic power consumption, which overstates static at operating frequencies greater than 10MHz, resulting in total power consumption being doubled or tripled.

 

 

Unused Entrances / Gates

When the inputs of a TTL circuit are left unmanned, they behave as if they were at a high logic level. However, this practice is not recommended, because via the non-driven inputs it is possible to couple the noise in the circuit. All inputs should be driven from a valid logic level:

  • A) Unused inputs of a gate used can be connected in parallel with inputs of the same gate, depending on the logic function.
  •  
  • B) Unused inputs can be connected to a voltage source: direct to GND or RS 1KΩ to VCC (RS resistance protects the input from overvoltages).
  •  
  • C) In the unused portions (gates) of a TTL integrated circuit, the inputs are connected in such a way that the outputs of these parts are constantly in a high state. This connection reduces power consumption, since it is ICCH

 

 

Various TTL Logic Gates

The standard TTL 74xx family of digital circuits includes a variety of logic functions in addition to the NAND core gate, thus facilitating the design of systems with fewer integrated circuits, fewer interconnection lines and better electrical characteristics. In this section we present the circuits of some of these logic functions.

TTL AND Gate

Figure 2-16

 

Figure 2-16 shows the circuit of a TTL AND gate (7408). The AND gate circuit is similar to NAND, with the addition of an additional inversion step (shaded area in the figure).

The passages, which are connected to gates A and B of the gate, are not related to the logic function of the gate. Their purpose is to protect inputs from negative voltage spikes caused by changing the signal level from high to low. The protection diodes limit these spikes to about -0.75V and absorb part of the signal energy to avoid potential oscillations when changing the input level. All TTL circuits include protection diodes at their inputs.

Figure 2-17 shows the circuit of a standard TTL NOR gate (7402). This gate consists of two parallel sections (shaded sections in Figure 2-17), each of which includes the basic input and guide circuit. Instead, the totem-pole output circuit is common.

When at least one input is in high logic state, the corresponding input transistor (T1A or T1B) is in reverse mode and the corresponding transistor (T2A or T2B) in saturation. Therefore T4 is cut off, T3 in saturation and output in low state.

When all inputs are at a low level, T1A and T1B are in saturation and T2A and T2B are cut off. So T3 is cut off, T4 is running and the output is in high state.

TTL NOR Gate

Figure 2-17

 

If the T1A and T1B input transistors are replaced by a multi-emission transistor, the logic function "AND-OR-INVERT" results.

In addition to the various logic functions, TTL gates with outputs other than the conventional totem-pole are available. Figure 2-18 shows a reversing gate with open collector output (7405), which allows it to be connected to wired-AND schemes.

TTL gate with open output collector

Figure 2-18

 

Instead of the classical totem-pole shape, the potential elevation transistor (T4) has been removed from the gate of Figure 2-18. To produce the high logic level, an external RPULLUP resistance (passive lifting element) is required to the VCC.

TTL gate with three-state output

Figure 2-19

 

By using gates with three-state outputs, it is possible to connect multiple outputs to a common bus. Figure 2-19 shows a TTL gate with three-state output. When the control input (G) is at a high level, the gate displays the input signal A at the output Y. With G at a low level, the transistor T1 is saturated, thus cutting the transistor array from T2 to T3. Also, the low level of G leads to cut-off and T5, T4. Hence the output Y is not driven by either VCC or GND.

 

 

Logic TTL Families

Standard TTL digital circuits (74xx, year of introduction 1968) formed the basis for a number of newer TTL subfamilies, the main features of which are described below.

The first variants of the standard TTL circuits were presented in two forms: a) the 74H series at almost twice the speed of standard TTL but also twice the power consumption; and b) the 74L series with a power consumption of only 10% but only 25% Of the TTL standard. The difference in power consumption and speed compared to standard TTL circuits was due to the choice of higher or lower resistor values ​​(for reduced power consumption or higher speed, respectively). The 74H and 74L series were soon replaced by more advanced TTLs.

 

 

Schottky TTL Logic Gates

The first TTL sub-family, which incorporated a series of technological advances in its circuits, was the Shottky TTL series (74S, year of introduction 1970). The circuits in this series use transistors and Shottky diodes.

A Schottky diode is formed in the metal and semiconductor contact. The static characteristics of the Schottky passage are similar to those of the p-n passage, but the correct polarization voltage of the Schottky passage is at 0.4-0.5V. Also the Schottky diode has a faster response because it does not have storage time. Using a Schottky diode between a base and a collector of a transistor (Figure 2-20a), we prevent the transistor from entering the saturation region by not letting the base-collector contact sufficiently polarized: Figure 2-20a if VBE = 0.75V and VD(Schottky) = 0.5V, then VCE = VBE-VD(Schottky) = 0.25V and the transistor is out of saturation. The Schottky transistor-diode combination is referred to as "Schottky transistors" and exhibits very fast transitions due to non-saturation.

Schottky TTL Gate

Figure 2-20

 

The basic form of a Schottky TTL (74S) gate is illustrated in Figure 2-20c. The gate transistors (except T4) are Schottky type, which increases gate speed. Protective diodes are also Schottky type, reacting faster on voltage spikes than normal diodes.

The TTL gate of Figure 2-20c includes some additional devices:

A) In the output stage, the elevation of the potential is achieved by a pair of Darlington transistors (T4 and T5). The Darlington pair increases the average current provided by the gate exit when going to high gear. Resistance R4 restricts the supplied current to standard TTL gates, but in the case of the Schottky TTL gate, the Darlington pair maintains the maximum current supply over a wider output voltage range. The Darlington pair output impedance is very low (typical 10Ω).

Due to the combination of T4 and T5, addition of diode D to the totem pole is no longer required. Resistance R5 is used to discharge the base of T4. An additional property of the Darlington pair is that T4 never enters the saturation range: always VCE5 > 0 and since VCB4 = VCE5, the T4 collector base contact is never polarized correctly to function at saturation. For this reason, the T4 of Figure 2-20c is of the simple type and not Schottky.

B) Transistor T6 together with resistors R2 and R6 form the so-called squaring circuit or active pulldown of output voltage (Figure 2-20b). This circuit replaces the base T3 base TTL resistance. In the latter (see Figure 2-6), T2 starts to run before T3 resulting in a gradual drop in voltage at the base of T4 and output respectively. With the quadrature circuit, when T2 starts to run, there is no path for the IE2 collector current to the ground only when T6 and T3 begin to drive. This avoids the gradual drop in the output voltage and ensures a steady transition to the low level.

The quadrant circuit achieves a narrower transition band from one level to the other and improves the noise margins for the low output state. Also, when T2 passes off, the charge at the base of T3 feeds the base of T6 and is thus removed through the T6 collector, leading to faster T3 cut-off.

Using small resistance values ​​and improved manufacturing technology, 74S gates were three times faster than standard TTL gates, but consumed twice the power.

 

 

LS TTL Logic Gates

The low-power Schottky 74LS (low-power Schottky, 1975) was established as the standard for general purpose low power TTL systems. Figure 2-21 shows the basic structure of an LS TTL gate.

As shown in Figure 2-21, the LS TTL gates returned to the DTL type structure with discrete passages (D1 and D2 in Figure 2-21), eliminating the multi-emission transistor. The reasons for this change are the following:

A) Improved manufacturing technology (6μm characteristic size) allowed the construction of diodes with dimensions significantly smaller than the multi-emission transistor. Smaller dimensions resulted in reduced parasitic capacities and increased operating speed.

B) The Schottky type transducer (Q1 in Figure 2-21) never enters the saturation range, so it does not require a quick removal of its base load through a multi-emission transistor.

In Figure 2-21, diodes D3 and D4 accelerate the transition of the output from high to low logic. D3 accelerates the transition of T4 to cut, while D4 drains current from external load at the time of transition.

LS TTL gate

Figure 2-21

 


The LS TTL gates were running at the same speed as the standard TTL but with a power consumption of only 1/5 of the standard TTL, making them ideal for general purpose design.

 

 

Advanced TTL Gates

The latest families of TTL integrated circuits appeared on the market in the 1980s. These families further improved the design of the LS TTL gates with additional circuits and used advanced manufacturing methods (3μm) for the time. These families were:

A) 74AS (Advanced Schottky, Texas Instruments). This fast-growing series was developed as a development of the 74S Series.

B) 74ALS (advanced low-power Schottky, the same company) as an improvement to the 74LS series. This series has the lowest delay-power product from all TTL families and improved driving capability.

C) 74F Series (Fairchild Semiconductor FAST TTL) with performance and power consumption between 74AS and 74ALS.

In Table 2-3 below are typical typical sizes of the different TTL families:

 

TTL family

74

L

H

LS

S

ALS

AS

F

propagation delay (ns) C L = 15pF

9

33

6

9.5

3

4

1.7

2.5

Power consumption (mW)

per gate

10

1

23

2

20

1.2

8

4

fanout

10

20

10

20

20

20

40

10


Table 2-3

 

By completing the presentation of TTL digital circuits, it should be noted that modern circuits no longer use this type of circuits, as CMOS technology (Chapter 3) is significantly superior to integration, low cost and reduced power consumption. Circuits with bipolar transistors are mainly used in output stages (BiCMOS technology) due to their increased driving capability against CMOS circuits.

Bipolar transistors are also used in logic circuits at very high operating speeds (GHz), but in different devices than in TTL circuits. These circuits are described in the following section.

 

 

Emitter Conjugate Logic (ECL)

In the circuits examined so far, bipolar transistors are used as switches, either operating in the saturation range or cut-off. In addition, bipolar contacts show relatively large voltage swings.

A different family of logic circuits with bipolar transistor, called "emitter coupled logic (ECL), uses the transistors in the active single region (without entering the saturation region), as well as smaller potential changes between the two logic states .

The transistors of the ECL circuits have smaller dimensions than the TTLs and hence smaller parasitic capacities. In addition, the functional characteristics of the transistors are different from those shown in previous sections: in the active region the contact voltage BE is about 0.8V or slightly higher.

ECL circuits are the fastest commercial logic circuits with a propagation delay less than 1ns and an operating frequency greater than 1GHz.

 

 

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