Digital Circuits with Bipolar Transistors Tutorial (page 3)

  

 

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⚛ The bipolar contact transistor ⚛ Propagation Delay ⚛ ECL Basic Gate (OR / NOR)
⚛ Early digital logic circuits ⚛ Power consumption ⚛ ECL Transfer curve (OR & NOR)
⚛ Diode-transistor logic (DTL) ⚛ Unused Entrances / Gates ⚛ ECL Driving ability
⚛ DTL gate power ⚛ Various TTL logic gates ⚛ ECL Propagation Delay
⚛ Logic transistor-transistor (TTL) ⚛ Logic TTL families ⚛ ECL Power consumption
⚛ NAND TTL Gate Function ⚛ Schottky TTL logic gates ⚛ ECL Differential signal transmission
⚛ Standard TTL standard features ⚛ LS TTL logic gates ⚛ Use of Positive Feed (PECL)
⚛ Logic levels and noise margins ⚛ Advanced TTL Gates ⚛ Logic ECL families
⚛ Driving ability ⚛ Emitter Conjugate Logic (ECL)  

 

 

 

ECL Basic Gate (OR / NOR)

The ECL basic gate (OR / NOR) circuit is illustrated in Figure 2-22:

Typical Circuit of Gate ECL (OR-NOR)

Figure 2-22

 

The more positive supply voltage (VCC) is connected to the system's ground (0V), while the negative power supply (VEE) is connected to -5.2V. The VCC voltage is used as the reference voltage for the logic input and output levels, typical values ​​of which are:

 

Low level: -1.75V

High level: -0.89V

 

A. Input circuit: It consists of a differential amplifier, which is formed by the input transistors (T1, T2 and T3) on one side and the reference voltage transistor T4 (VBB) on the other. The transistors have a common emission connection (coupled emitters, from which the name of the ECL circuits). The input circuit leads the bases of the output transistors (T6 and T7), depending on the voltage difference between the inputs and the VBB, which is what implements the logic function of the gate.

The operation of the differential amplifier is as follows:

A) If all inputs are in low logic state (-1.75V), the transistors T1, T2 and T3 are cut off. This is because, with VBB = VB4 = -1.29V and VBE4 = 0.8V, it is VE = VBB - VBE4 = -2.09V and VBE1,2,3 = -1.75V - (-2.09V) = 0.34V. This value of VBE1,2,3 is less than the required treatment trend, so T1, T2 and T3 are actually cut off and T4 is conducting.

B) When an input (even input A) goes to a high logic level (-0.89V), then VBE1 = -0.89V - (-2.09V) = 1.2V and the transistor T1 starts to run. Then the VE voltage is -0.89V - 0.8V ≈ - 1.7V, driving the T4 to a cut. The RC1, RC2 and VBB resistors are selected in such a way that the transistors T1, T2, T3 and T4 never enter the saturation range.

This differential function (one side runs while the other is cut off and vice versa) leads complementarily to the output transistor bases (T6 and T7). Differential operation results in the near constant current flow from VCC to VEE through RE in any logic output state, even when switching from one state to another.

An additional advantage of the input circuit is that it operates based on the difference of inputs and VBB s and not the absolute value of input voltages. If there is a common noise in the system, affecting both sides equally (inputs and VBB s), then this noise does not change their difference and is therefore discarded (common mode rejection).

B) Supplementary Output Circuit: This is a two-emitter follower circuit, where the VOR and VNOR outputs follow the voltage at the base of T6 and T7, respectively, reduced by VBE. Through the output transistors, the gate provides current in both logic states, displaying a low impedance of impedance equal to 6-7Ω.

A) If all inputs are in a low logic state, the input transistors are cut off and T4 is running. Current flows from VCC to VEE via RC2, T4 and RE. Considering the base currents of all transistors negligible are:

 

Formula4   IRC2 = IE = ( VE - VEE ) / RE = 3.11 / 777 ≈ 4mA

 

VRC2 = - (IRC2 x RC2) = - (4mA x 245Ω) = -0.98V

 

VOR = VB6 - VBE6 = VRC2 - VBE6 = -0.98V - 0.77V ≈ -1.75V (low)

 

With a typical VBE6 = 0.77V for 6mA output current.

The voltage at the base of the T7 is slightly lower than the VCC (≈ -0.05V) due to the minimum leakage current. For an output current of 22.5mA the typical value of VBE7 is about 0.84V and the VNOR output is:

 

VNOR = VB7 - VBE7 = -0.05V - 0.84V ≈ -0.89V (high level)

 

B) If at least one input is at a high level, the corresponding transistor is on and T4 is cut off. As before,

 

IE = ( VE - VEE ) / RE = -1.7+5.2 / 777 ≈ 4.51mA

 

VRC1 = - (IRC1 x RC1) = - (4.51mA x 217Ω) ≈ -0.98V

 

So VOR = -1.75V and VNOR = -0.89V.

 

As shown in Figure 2-22, the output circuit is driven by a different VCC terminal than the rest of the circuit. This connection reduces the effect of large driving currents on internal logic circuits.

C) Reference Voltage Generation Circuit: This circuit produces the reference voltage VBB (-1.29V), which is used in the differential amplifier to compare input voltages. For the proper operation of the ECL gate and the maximization of the noise margins, the VBB voltage must be constantly between the two logic states.

The voltage of bi-polar p-n polar contacts, when emitted by a constant current, depends on temperature, at a rate of -2mV / oC. Therefore, as the temperature rises, the logic levels of the ECL gate are shifted to ground. The noise margin is reduced and after a certain temperature (about 60°C) the gate is malfunctioning.

The reference voltage circuitry ensures that the VBB follows the changes of the logic states according to the temperature, always maintained in the middle.

 

 

ECL Transfer Curve

Figure 2-23 illustrates the two characteristic transform curves (OR and NOR) of the ECL basic gate:

Typical ECL Transfer Curve

Figure 2-23

 


For ECL circuits, except for the worst case scenarios (VIL(max), VIH(min), VOL(max), VOL(min)) which determine the correct transmission of signals, Produced input / output levels (VIL(min), VIH(max) and VOL(min), VOL(max)).

The levels shown in Figure 2-23 apply to an ambient temperature of 25 ° C. Data sheets of ECL integrated circuits are given the logic levels at various temperatures (eg -30, +25 and + 85οC). It is also given the change of output states in relation to the increase of VEE:

 

ΔVOH / ΔVEE = 0.016 and ΔVOL / ΔVEE = 0.250

 

From the values ​​in Figure 2-23, the ECL gate noise margins are determined:

 

NMH = VOH (min) - VIH (min) = -0.98 - (- 1.105) = 125mV

 

NML = VIL (max) - VOL (max) = -1.475 - (- 1.63) = 155mV

 

With a shorter margin at high-state.

In normal operation the voltage swing range is relatively small and equals to 800mV. The small switching range, along with the low ECL gate output impedance, helps reduce noise and crosstalk interactions.

When the logic output levels are outside the transition area (gray area in Figure 2-23), their values ​​are independent of Vin except VNOR, which continues to decrease as Vin grows. This is because the corresponding input transistor drives more current as Vin increases, resulting in a VB7 voltage drop (Figure 2-22). In newer ECL gates, this phenomenon has been eliminated.

 

 

ECL Driving Ability

An ECL gate output produces high potential through the T6 or T7 transistor (for OR and NOR outputs respectively). The output impedance is very low (6-7Ω), which means that the gate is able to supply a large amount of current in this state.

Interconnection of ECL gates

Figure 2-24

 

The guided gate has at its input a 50K resistor, which is used to keep the input at a low logic level when it is unconnected. When the input is in a high logic state, the current flowing through this resistance is negligible, while with the base current of the input transistor it does not exceed 450μA.

When the gate output is at a low level, there is no conductive path between the line and the VEE. For this reason an external RT resistor is required to remove the load from the driven input and produce the low level (the 50K input resistance is very high and can not be used for this purpose). A common tactic is the use of RT = 50Ω for connection with intermediate termination voltage VTT = -2V (Figure 2-24). The choice of 50Ω is not accidental, as will be shown below.

With RT = 50Ω and VTT = -2V there is a constant current supply from the ECL gate

 

In low state: (VOL(type) -VTT) / RT = (-1.75 - (- 2.0)) / 50 = 5mA

 

In high mode: (VOH(type) -VTT) / RT = (-0.9 - (- 2.0)) / 50 = 22mA

 

All ECL gates can continuously provide at least 22.5mA for driving an equivalent resistive load of 50Ω at each output.

The speeds of the ECL gates are so great that the interconnection line between two gates behaves like a transmission line (see Chapter 5). This practically means that at all times the voltage is not the same at all points in the pipeline. The voltage pulses are transmitted at a specific speed along the duct and are reflected at its ends. These reflections reduce the quality of the signal and can cause reasonable errors. To reduce reflections, it is necessary to "terminate" the line, ie to connect a resistance at the end of the conductor to a constant supply voltage. This resistance should be as close as possible to the characteristic resistance of the conductor, which for printed circuits is about 50Ω. Thus, the RT value of Figure 2-24, which terminates the interface cable, is usually selected at 50Ω.

 

 

ECL Propagation Delay

The ECL gates of the base line 10K show a typical propagation delay equal to 2ns. The propagation delay is increased depending on the output capacitance of the output, mainly at the downward edge of the output signal.

When the output goes to high state, the gate provides current to the driven load through the 7Ω impedance of the output transistor. The loading of the driven capacities is very fast, practically independent of their size.

However, if the output is low, the voltage at the base of the output transistor is momentarily lower than the emitter voltage and the transistor is cut off. Figure 2-25 illustrates the theoretical electrical equivalent at this time: driven capacities are discharged only through the RT resistance until the voltage at the output transistor emitter reaches VOL. Then the transistor starts to go again, keeping the output at the low logic level.

Τransition to low level

Figure 2-25

 

The discharge rate of CL through RT is less than the charge rate through the output transistor, hence the RT, which determines the total gate propagation delay. In practice, each driven input adds 0.1ns to the propagation delay with RT = 50Ω, VTT = -2.0V. If RT = 100Ω, the increase in propagation delay per driven input is 0.2ns.

Due to the lack of a totem pole at the exit of the ECL gates, it is possible to connect the wired-OR logic of several outputs of different gates together. In such a connection it is sufficient for a gate outlet to be in a high logic state to drive the total output to a high level. However, the multi-output interface degrades gate speed (adding about 50ps per add-on to the propagation delay) and practically should not exceed the six interconnected outputs.

 

 

ECL Power Consumption

Power consumption of an ECL gate is calculated without driving load (unconnected outputs). Much of the power is consumed in the input circuit (differential amplifier). As calculated in paragraph 2.4.1, the current flowing through the RE of Fig. 2-22 is 4.0mA and 4.51mA for the two differential amplifier states with an average of 4.26mA. Therefore, the power consumption in the input circuit is (-) 5.2V x 4.26mA ≈22mW. Additional power consumption occurs in the reference voltage supply circuit, resulting in typical consumption per gate of the basic ECL 10K series equating to 25mW.

However, as in the case of propagation delay, the total circuit consumption is greater due to the additional power consumed in the output transistors. This consumption is highly dependent on the RT and VTT values. Average power consumption values ​​in the output circuit are given in Table 2-4 below:

 

RT

VTT

power consumption

100O

-2.0V

7.5mW

50W

-2.0V

15mW

510O

-5.2V

9.7mW

270O

-5.2V

18.3mW

 

Table 2-4

 

The power consumption described so far is static when the gate exit is in a steady state. For ECLs of the base line 10K, the dynamic power consumption is very small in relation to static power consumption due to the way the gate operates, the small capacities of the transistors and the absence of a totem pole at the gate exit.

 

 

ECL Differential Signal Transmission

One of the most important advantages of using ECL circuits is the ability of differential transmission. With this technique each signal is transmitted to the next gate using two lines. Each line carries the symmetrical signal of the other and the final result is the difference between these two signals. The main characteristic of differential transmission is the common mode rejection, ie the alterations that will occur simultaneously on the two lines, as long as the difference between the two signals is not affected.

ECL gates are ideal for differential signal transmission because they also provide the normal and inverted form of the output signal (Figure 2-26):

 

Differential signal transmission with ECL circuits

Figure 2-26

 

In Figure 2-26, the illustrated differential receiving circuit, which calculates the difference of the two input signals, is implemented as a normal ECL gate, with the only difference being the use of Vin and Vin 'in the differential input amplifier instead of Vin and VBB Of Figure 2-22.

 

 

Use Of Positive Feed (PECL)

In normal operation, ECL circuits use a negative voltage supply (VEE) (-5.2V), while VCC (0V) is used as the reference level. However, there are cases where it is desirable to combine ECL circuits with + 5V technologies, such as TTL and CMOS. Examples of such cases are:

A) In a typical high-speed data processing system, the data is entered / output serially at a high rate (> 200MHz). Conventional TTL / CMOS circuits can not operate at this frequency. ECL circuits convert serial input into parallel lower frequency data (<50MHz), which are then output to the TTL / CMOS master.

B) The use of ECL circuits in the interconnection of subsystems, consisting of TTL / CMOS logic circuits, reduces the noise generated and increases the reliability of the transmission (especially when the latter occurs in a differential manner).

C) Distributing clocks to a high speed system is safer and displays the minimum difference between clock skew at different points in the system when using ECL driving circuits.

The combination of ECL circuits and positive supply voltage circuits would require the simultaneous use of two different supply voltages (eg + 5V and -5.2V) and possibly another VTT termination voltage. However, the ECL circuits can also operate with a positive supply voltage, provided that the potential difference between VCC and VEE is within the preset limits.

In this "positive" mode (PECL - positive ECL), the VCC is connected to the 5V and VEE to the ground. All ECL gates can operate in this way, generating output levels increased by VCC. For example, while the normal VOH(max) = -0.81V, in PECL mode with VCC = 5V is VOH(max) = 5 - 0.81 = 4.19V.

Because the logic levels of the ECL circuits use the VCC reference voltage, it is necessary to minimize the noise in this feed line. Any noise in the VCC will appear to be the same at the reasonable levels of the gate. In addition to the use of decoupling capacitors between VCC and ground, the supply of ECL circuits should be as isolated as possible from the supply of TTL / CMOS circuits, which generate more noise at logic transitions.

 

 

Logic ECL Families.

The first ECL integrated logic circuits (MECL I) appeared in 1962. These circuits had an 8ns propagation delay, far greater than the conventional logic circuits of that time. With the advancement of technology, new ECL families appeared, the characteristics of which are listed in Table 2-5:

 

logic family

MECL II

MECL III

10K

10KH

100K

import year

1966

1968

1971

1981

1985

typical propagation delay (ns)

4

1

2

1

0.75

rise / fall time (ns)

 

1

3.5

1.8

0.7

power consumption per gate (mW)

20

60

25

25

50

operating frequency (MHz)

70

500

125

250

400

 

Table 2-5

 

The MECL III family remains one of the fastest on the market today. The high speed of operation, but especially the very short-time up and down of the MECL III gates required advanced system design and advanced techniques to maintain the integrity of the signal integrity. The difficulty in using these gates has led to the development of families at a controlled anode-descent rate, such as the 10K series, which is the basis for comparison for the newer ECL circuits.

The ECL 100K series includes advanced reference voltage generating circuits, which make the logic levels independent of temperature variations and VEE variations, thus improving the functional characteristics of the ECL gates and increasing the noise margin. The most recent logic families ECL, ECLinPS (1988) and ECLinPS Plus (1999) achieve maximum propagation delay of 500ps and 350ps, respectively. These gates can operate at a frequency greater than 3GHz.