Digital Circuits with Bipolar Transistors Tutorial



At this page (1) Page 2 Page 3
⚛ The bipolar contact transistor ⚛ Propagation Delay ⚛ ECL Basic Gate (OR / NOR)
⚛ Early digital logic circuits ⚛ Power consumption ⚛ ECL Transfer curve (OR & NOR)
⚛ Diode-transistor logic (DTL) ⚛ Unused Entrances / Gates ⚛ ECL Driving ability
⚛ DTL gate power ⚛ Various TTL logic gates ⚛ ECL Propagation Delay
⚛ Logic transistor-transistor (TTL) ⚛ Logic TTL families ⚛ ECL Power consumption
⚛ NAND TTL Gate Function ⚛ Schottky TTL logic gates ⚛ ECL Differential signal transmission
⚛ Standard TTL standard features ⚛ LS TTL logic gates ⚛ Use of Positive Feed (PECL)
⚛ Logic levels and noise margins ⚛ Advanced TTL Gates ⚛ Logic ECL families
⚛ Driving ability ⚛ Emitter Conjugate Logic (ECL)  




The Bipolar Contact Transistor

Early digital circuits used the bipolar junction transistor (BJT) to implement the various logic functions. In digital circuits, the transistor is primarily used as a switch whose operating characteristics are described below. The analysis is based on NPN transistors, but the PNP transistors are the same.

The BJT transistor as a switch

Figure 2-1


Figure 2-1a illustrates a typical NPN type bipolar transistor. The current flowing through the base of the transistor is denoted as IB while that through the collector as an IC. The operating ranges of this transistor are listed in Table 2-1 below:




contact BE

contact BC

currents IB, IC



forward biased

reverse biased

IC = b IB

b = current gain factor of transistor


reverse biased

reverse biased

IB = 0, IC = ICEO

ICEO = Reverse collector saturation current, practically 0


forward biased

forward biased

IC < b IB

voltage between collector and emitter  VCE ≈ 0.2V or lower

Reverse mode

reverse biased

forward biased

IE = bR IB

bR = Gain coefficient reverse Operation


Table 2-1


As a switch, the bipolar contact transistor is generally either cut-off (open circuit) or saturation (closed switch). In the active region, it passes for a short time, during transitions from saturation to cutback or vice versa. Reverse operation is a special case to be considered later.

Figure 2-1b illustrates a theoretical reversal circuit, which will be used to describe the switching operation of the transistor.

  1. 1) Initially, let the input Vi = 0V (low logic level). Based on the data in Table 2-1, the transistor is cut off and is IB = 0, IC = 0, VBE = 0V while Vo = VCE = VCC (high logic level).
  3. 2) If the Vi increases to approximately 0.6V, the base-emitter contact is polarized correctly and the transistor is at the limit of the treatment. Then it is VBE = 0.6V while IB's and IC's are just beginning to become larger than 0.
  5. 3) With a further increase of Vi, the transistor enters the active operating range. Then apply: VBE = 0.7V and IC = bIB.
  7. 4) With a higher Vi increase, the transistor is in the saturation range, where VBE ≈ 0.75V, IC is less than bIB and VCE = Vo ≈ 0.2V (low logic level).

The Vo output changes state with respect to Vi with a certain delay, which is caused by the accumulation of charge in the parasitic capacitance of the base-emitter contact. The most important delay is due to the discharge of this capacity when the transistor passes to the cut-off and is called storage time.



Early Digital Logic Circuits

The first form of integrated logic circuits used the circuit of Figure 2-2 and was called "resistor-transistor logic" (RTL, early 1960s).

RTL Gate (NOR)

Figure 2-2


The circuit of figure 2-2 implements the logic function NOR: when inputs A and B are at a low level, the transistors T1 and T2 are cut off and output at a high level, while at any other input combination the output is low level.

RTL logic gates showed a time-efficient propagation delay and power consumption (12ns and 16mW respectively) but at the same time they had a very low noise level (~ 0.4V) and driving capability (maximum fanout = 5). So they were soon replaced by DTL (diode-transistor logic) integrated circuits.



Diode-Transistor Logic (DTL)

The basic circuit of a NAND DTL gate is illustrated in Figure 2-3:

Typical Circuit of DTL Gate (NAND)

Figure 2-3


In summary, the operation of the circuit of Figure 2-3 is as follows:

  • A) If all Vi inputs are in high state (5V), the corresponding input diodes are cut off. Current through resistor R flows to the base of transistor T1 and leads to saturation. Vo output voltage equals VCE1(sat) = 0.2V (low logic level).
  • B) If at least one input is in low state (0.2V), then the voltage at point A of Figure 2-3 equals VA = 0.2V + VD = 0.95V, assuming the current flowing through the input is enough to The voltage at the ends of the corresponding diode equals 0.75V.

The minimum required VA voltage to start T1 is:


VA = VD1 + VD2 + VBE1 = 3 x 0.6 = 1.8V


With a voltage of 0.6V correct polarization due to the minimum current. Therefore, with VA = 0.95V, T1 is cut off, the current through D1, D2 and RB passes to ground, while the output via RC is driven at 5V (high level).

When T1 is in saturation and one input goes to low level then D1 and D2 momentarily will be cut (VA = 0.95V, VB = 0.75V). If there was no RB, the charge at the base of T1 could not be moved to the ground and T1 would be too slow to cut. Through RB, the capacity of the T1 base is discharged, achieving a reasonable transition time from low to high output level.



DTL Gate Power

Assuming that the DTL gate leads similar gates, it is:

  • A) When the output is at a high level, there is no current flowing towards the guided gates (the input diodes are inversely polarized) and the influence of the number of gates being driven is negligible.
  • B) When the output is at a low level, current through the inlets of the driven gates flows to the collector of T1 (Figure 2-4).

Low output level

Figure 2-4


The gate can lead multiple inputs as long as T1 does not come out of the saturation range (IC1 is less than bIB1 and VCE1(sat) = 0.2V). This practically means that either the IC1 must be kept small (large R value), or IB1 must be large (large RB value), or the T1 coefficient b must be large.

Dissemination delay: DTL gates generally apply to tPLH > tPHL (2 to 3 times). The transition of the output from high to low is quickly achieved through the T1, which is in saturation. Otherwise, the driven capacities are slowly charged through the RC and the transition delay is additionally added to the time to discharge the T1 base through the RB.

Typical DTL gate circuit.png

Figure 2-5


Figure 2-5 illustrates a typical DTL gate circuit.

In this circuit the diode D1 has been replaced by the transistor T2. This transistor operates in the active area and provides an increased amount of current at the base of T1, thus increasing the gate's driveability.

Typical values ​​of the gate function characteristics of Figure 2-5 are propagation delay: 75ns, power consumption: 10mW and fanout: 45. The low operating speed of the DTL circuits eventually led to their replacement by the transistor-transistor logic (TTL) .



Transistor-Transistor Logic (TTL)

The transistor-transistor logic (TTL) logic was the main technology for the manufacture of digital circuits with bipolar transistors. TTL circuits have improved the main disadvantage of DTL logic, which is reduced operating speed. The TTL gate can be seen as a transformation of the DTL circuits.

The basic TTL circuit, a NAND gate, is shown in Figure 2-6. The portions of this gate are described below.

Typical TTL Gate circuit (NAND)

Figure 2-6


A. Input Circuit

The basic input circuit consists of a multi-transistor T1 transistor. As shown in Figure 2-7a, this transistor equals the DTL gate structure with passages. A simplified plan view of a multi-emission transistor is illustrated in Figure 2-7b. The silicon surface required to construct the multi-emission transistor is less than the surface required by the distinct diodes of the DTL inputs.

The operating conditions of the multiple emission transistor are as follows:

  • A) When at least one input is at a low logic level, then the base current of the transistor goes to the emitter of this input (Figure 2-7c). The transistor is in saturation since the IC current is too small (it comes from the base of transistor T2 of Figure 2-6). If inputs are high, they can practically be cut off.
  • B) When all inputs are at a high logic level (Figure 2-7d), then the transistor is in the reverse mode. The current from the base of the transistor (IB) and from the inputs (IE) is directed to the transistor collector. Because IE = bRIB with standard value bR = 0.02, the collector receives mainly current from the base of the transistor and only 2% from the inputs.

Multi-emission input transistor

Figure 2-7

As shown in Figure 2-6, the multi-emission T1 input transistor is directly connected to the base of transistor T2. This direct connection allows for rapid discharge of the T2 base through the T1 collector when some input is in a low logic state. This connection is superior to the corresponding DTL gate (see section 2.2.1), increasing the TTL gate speed.


B. Driving circuit

It consists of transistor T2 and resistors RC2 and RE. It is a typical phase splitter circuit, which leads in addition to transistors T3 and T4 (ie when one conducts, the other is cut off and vice versa). As mentioned previously, T2 is driven by the T1 collector.


C. Totem-pole output circuit

It consists of two active lifting elements (T4) and a potential drain (T3). These two transistors are driven alternately by the transistor T2, ie in a stable output state there is no conductive path between VCC and GND:

  • A) When T4 runs and T3 is cut off, the output is connected to the high level (VCC) via the RC4 resistor (130Ω).
  • B) When T3 runs (in the saturation range) and T4 is cut off, then the output voltage equals VCE3(sat) ≈ 0.2V (low logic level).

When switching the low to high logic output, the capacities of the driven loads, which are connected to the gate outlet, are charged through the RC4 low resistance (130Ω). The low resistance value significantly reduces the time required to load the capacities, accelerates the change of state and increases the drive's output capacity.

Also, because in stable output state there is no current flow between VCC and GND via T3 and T4, the small value of RC4 does not affect the power consumption of the circuit.

The way to go from low to high can be compared with that of the DTL gates, in which the elevation of the potential is achieved through a passive element (pullup resistance - figure 2-3). This resistance must be large enough (some KΩ) to limit the current (and corresponding power consumption) flowing constantly through it from VCC to GND when the output is at a low level. On the other hand, the high drag pullup value lengthens the charging time of external capacities when switching the output from low to high logic.

Comparison of the totem-pole output stage of a TTL gate with the corresponding DTL passive elevation step demonstrates the advantages of the first: the totem-pole step combines the advantages of speed and reduced power consumption.

As mentioned previously, in the totem-pole output stage at steady state output only one of the two transistors T3 and T4 is conducting. When changing the state, however, the two transistors are instantaneously at the same time, causing sharp current peaks between the supply lines (VCC and GND). In the co-current mode, only the RC4 resistor exists between VCC and GND, which ensures that no excessive short-circuit current will pass over this short period of time.

The usefulness of D path is completely different and will be explained in the next paragraph.



NAND TTL Gate Function

Suppose an input of the TTL NAND basic gate is at a low logic level of 0.2V (Figure 2-8):

TTL NAND gate Basic Function 1

Figure 2-8


As mentioned in the previous paragraph, T1 is in saturation and the trend in its collector equals:


VC1 = Vi + VCE1(sat) = 0.2V + 0.2V = 0.4V


The voltage at the base of T2 is equal to VC1, which means T2 is cut off (at best it would need VBE2 = 0.6V). So there is no current in the T2 emitter or the base of T3. Therefore, T3 is also cut off.

Instead, the T4 conducts (in the active region) and the gate provides current to the loads connected to the Vo output via the RC4. If the output is unconnected, then IB4 ≈ 0, IE4 ≈ 0, the voltage drop on RC2 ≈ 0, VBE4 and VD ≈ 0.6V (because of the minimum current) and:


Vo = VOH = VCC - VBE4 - VD = 5V - 0.6V - 0.6V ≈ 3.8V (high level)


If all inputs are at a high logic level (3.8V), then the state of the gate is described in Figure 2-9.

T1 is in reverse mode and the base current of T1 flows to the base of T2. This current is enough to lead T2 to saturation. Through RC2 and T2 flows a quantity of current to the base of T3. Because of the resistance RE, most of this current is driven to the base of T3, which is also in saturation. Thus the Vo output voltage equals:


Vo = VOL = VCE3(sat) ≈ 0.2V (low level)


The trend at the base of T4 is equal to:


VB4 = VBE3(sat) + VCE2(sat) = 0.75V + 0.2V = 0.95V


Due to D path, in order to find T4 at the limit of treatment, we should:


VB4 > VCE3(sat) + VD(at treatment limits) + VBE4(at treatment limits) > 0.2V + 0.6V + 0.6V> 1.4V


Which is obviously not the case, so T4 is cut off.

The last inequality highlights the role of the D path because without it VB4 > VCE3(sat) + VBE4(in the treatment limits) > 0.8V would be enough to start T4, so in the current state the T4 excision would not be secured .

TTL NAND gate Basic Function 2

Figure 2-9



TTL Standard Features

TTL gates such as the NAND gate previously described were the first form of TTL circuits and are called standard TTLs. These gates are also known by their manufacturing code: 74xx, where xx describes the logic function of the gate. The main functional characteristics of the standard TTL gates are described below, as given by the manufacturers.



Logic Levels and Noise Margins

The logic levels set for standard TTL circuits are as follows:


















Table 2-2


The minimum noise margins are set respectively:


NML = VIL(max) - VOL(max) = 0.4V


NMH = VOH(min) - VIH(min) = 0.4V


The VOL, VOH values in Table 2-2 are worst cases. In practice, typical values under normal operating conditions are VOL = 0.2V and VOH = 3.4V and the corresponding noise margins are much higher than the ones determined, with the most critical low-level margin (NML) always being critical.

The VT threshold voltage of Table 2-2 is approximate and is not officially given by the manufacturers, with slight variations depending on the construction parameters of each gate.

Figure 2-10 shows the characteristic Vin / Vout transport curve for a standard TTL standard gate. The transfer curve is dependent on ambient temperature.

Typical voltage transfer curve TTL

Figure 2-10



TTL Driving Ability

A TTL gate provides (source) drain current to / from the entrances of the gates leading, depending on the logic state of the output.

A. When the output is at a low logic level (Figure 2-11), the gate drops the current through T3, which is in saturation.

Low output level

Figure 2-11


According to the Accrual Convention, the IOL is positive for the leading gate, while the IOL-driven is negative.

Current IIL comes from the base of T1 and is regulated by the RB resistance. Its guaranteed maximum value is IIL(max) = -1.6mA with Vin = 0.4V. Standard TTL gates are designed to drive 10 identical gates, so the maximum IOL(max) that submerges one output while remaining at a valid low level is set at 16mA.

Because the T3 transistor is in saturation, the impedance of the low ROL output is very small (standard 10Ω). The low ROL is an advantage both for fast and powerful driving of external loads, as well as for keeping low noise generated by the steep current flow during alternating states.

Figure 2-12 shows the VOL-IOL curve of a standard TTL gate.

Typical output curve VOL-IOL

Figure 2-12


B. When the output is at a high logic level (Figure 2-13), then the leading gate provides current through RC4, T4 and D. By convention, IIH is positive while IOH is negative.

High output level

Figure 2-13


The input transistor is in reverse mode and the input current IIH is relatively small. The maximum worst case value is IIH(max) = 40μA with Vin = 2.4V. Therefore, in order for a standard TTL gate to lead 10 similar inputs it should provide IOH = -0.4mA maintaining a valid high output level (> 2.4V).

Figure 2-14 below shows the VOH-IOH curve for a standard TTL gate.

Typical output curve VOH-IOH

Figure 2-14


In addition to the maximum IOH current, manufacturers' brochures give the value of the IOS short circuit current, which the gate can provide for a short time when its high logic output is shorted to ground. The values ​​given are -18mA (min) and -55mA (max).

The high output (ROH) output impedance is also low and ranges for standard TTL circuits between 50Ω and 70Ω.

Note: When two or more inputs of the multi-emitter transistor are connected together (led by the same signal, Figure 2-15), then:

A) If it is at a high level, the total current IIH is proportional to the number of inputs connected together (n x IIH).

B) If it is at a low level, then the total current IIL is set by the resistance RB and does not depend on the number of inputs.

Parallel input connection

Figure 2-15



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