This buffer amplifier`s overall harmonic dis tortion is a low 0.01 % or less at 3-V rms output into a 500-fl load with no overall feedback. The LT1010CT offers a 100 V/p.s slew rate, a 20 MHz video bandwidth, and 100 mA of output. A pair of JFETs, ]1 and J2 are preselected for a nominal match at the bias level of the linearized source-follower input stage, at about 0.5 mA. The source: bias resistor, R2, of ]1 is somewhat larger thao R3 so that it cao drop a larger voltage aod cancel the LT1010CT`s offset. J1 andJ2 provide ao untrimmed de offset of Â±50 mV or less.
Swapping ]1 and J2 or trimming the R2 value cao give a finer match. The circuit"s overall harmonic distortion is low: 0.01 % or less at 3-V rms output into a 500-fl load with no overall feedback. The circuit"s response to a Â± 5 V, 10kHz square-wave input, band-limited to 1 p.s, has no overshoot. lf needed, setting bias resistor R8 lower cao accommodate even steeper input-signal slopes and drive lower impedance loads with high linearity. The main trade-off for both objectives is more power dissipation. A secondary trade-off is the need for retrimming the source-bias resistor, R2.