Posted on Nov 26, 2012

When power is first applied, three things happen: light -driving transistor Ql is switched on due to a iow output from U2 pin 3; timer U1 begins its timing cycle, with the output, pin 3, becoming high, inhibiting U2`s trigger, pin 2, via D2; and charge current begins to move through R3 and R4 to Cl. When Ul`s output becomes low, the inhibiting bias on U2 pin 2 is removed, so U2 begins to oscillate, flashing the third light via Ql, at a rate determined by RS, R6, and C3. That oscillation continues unW the gate-threshold voltage of SCRl is reached, causing it to fire and pull Ul`s trigger, pin 2,low. With its trigger low, Ul`s output is forced high, disabling U2`s triggering.

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With triggering inhibited, U2"s output switches to a low state, which makes Ql conduct, turning on Il until the brakes are released. Of course, removing power from the circuit resets SCRl, but the rc network consisting of R4 and Cl will not discharge immediately and will trigger SCRl earlier. So, frequent brake use means fewer flashes.

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