Dual-Slope Integrating ADC

Posted on Feb 5, 2014

A column-parallel analog-to-digital converter was designed for use with CMOS active pixel sensors (APS). The design goals included simplicity, small size, moderate speed (>10kHz), current input, and reasonable accuracy (6-bits). The ADC was designed to get a rough digital output from pixels that serve some other primary function (image quality sen

Dual-Slope Integrating ADC
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sing, stereo vision, etc. ). The ADC was designed with a current input. This greatly decreases the area necessary to implement the ADC; a dual-slope ADC with a voltage input (from a high impedance source) requires a transconductance amplifier in order to integrate the voltage over time. The ADC works in three steps. During the first step switch S1 is turned on, resetting the capacitor to a known, fixed voltage. Switch S1 is then turned off. During the second step switch S2 is turned on for a fixed time period. The change in voltage on the capacitor is then directly proportional to the input current (which is assumed to be constant over the integration time). During the third step the capacitor is discharged with a known reference current I2. The time taken for the capacitor to reach the original reference voltage V1 is then directly proportional to the input current. This time is independent of the value of capacitor C1 (ignoring non-idealialities is the current sources). The cycle then repeats again. A more detailed schematic and layout can be seen in the appendix. The voltage on the capacitor is compared against the reference voltage using a latched comparator (the layout and schematic are shown in the appendix) [ [1] ]. The comparator is clocked 64 times (representing 6 bits) during the discharge cycle. The number of latches needed before a high output is reached represents the output value of the ADC. The design...

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