FPGA RS232 Serial Interface Circuit

Posted on Feb 5, 2014

The schematic for this project is a modified version of the CPLD dev board schematic. There are a few new parts added for this project and you can see the completed schematic for this project below. The main parts in the schematic are the CPLD Dev Board, MAX233a and 7 Segment Display. The RS232 interface circuit consists of the CPLD, it`s 25. 17

FPGA RS232 Serial Interface Circuit
Click here to download the full size of the above Circuit.

5 MHz crystal clock and the MAX233A. The MAX233A translates the +12v higher voltage RS232 signals into TTL +5v logic that the FPGA can understand. This protoboard for a cpld was developed by me a few years ago. It`s really just a PLCC CPLD in a socket with power and JTAG connectors for programming. This oscillator was chosen mostly at random. We needed some type of timing device to keep a reference to time and I had this one laying around. Generally if you can find a clock above 10 MHz you`ll be fine for this project.

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